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Searched refs:v_packed_data_32 (Results 1 – 2 of 2) sorted by relevance

/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_stream_integer_type.v27 logic [31:0] v_packed_data_32; register
124 v_packed_data_32 = {<<8{bit_in}};
134 {<<8{bit_out}} = v_packed_data_32;
156 v_packed_data_32 = {<<test_byte{bit_in}};
166 {<<test_byte{bit_out}} = v_packed_data_32;
178 v_packed_data_32 = 0;
194 $display("TEST: v_packed_data_32=%0h", v_packed_data_32);
227 …$display("v_packed_data_32=%0h, v_packed_data_32_ref=%0h", v_packed_data_32, v_packed_data_32_ref);
259 …$display(" %s v_packed_data_32=%0h, v_packed_data_32_ref=%0h", name, v_packed_data_32, v_packed_da…
321 …if (error_ == "") if (v_packed_data_32 !== v_packed_data_32_ref) error_ = "integer_vector_type bit…
H A Dt_stream_integer_type.out29 124 | v_packed_data_32 = {<<8{bit_in}};
63 …r ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32…
65 134 | {<<8{bit_out}} = v_packed_data_32;
125 156 | v_packed_data_32 = {<<test_byte{bit_in}};
129 156 | v_packed_data_32 = {<<test_byte{bit_in}};
133 156 | v_packed_data_32 = {<<test_byte{bit_in}};