Searched refs:v_packed_data_32_ref (Results 1 – 1 of 1) sorted by relevance
| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_stream_integer_type.v | 28 logic [31:0] v_packed_data_32_ref; register
227 …$display("v_packed_data_32=%0h, v_packed_data_32_ref=%0h", v_packed_data_32, v_packed_data_32_ref);
259 … %s v_packed_data_32=%0h, v_packed_data_32_ref=%0h", name, v_packed_data_32, v_packed_data_32_ref);
286 v_packed_data_32_ref = {bit_in[3], bit_in[2], bit_in[1], bit_in[0]};
321 …if (error_ == "") if (v_packed_data_32 !== v_packed_data_32_ref) error_ = "integer_vector_type bit…
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