Searched refs:v_packed_data_64 (Results 1 – 2 of 2) sorted by relevance
33 logic [63:0] v_packed_data_64; register125 v_packed_data_64 = {<<16{logic_in}};135 {<<16{logic_out}} = v_packed_data_64;157 v_packed_data_64 = {<<test_short{logic_in}};167 {<<test_short{logic_out}} = v_packed_data_64;179 v_packed_data_64 = 0;195 $display("TEST: v_packed_data_64=%0h", v_packed_data_64);231 …$display("v_packed_data_64=%0h, v_packed_data_64_ref=%0h", v_packed_data_64, v_packed_data_64_ref);262 …$display(" %s v_packed_data_64=%0h, v_packed_data_64_ref=%0h", name, v_packed_data_64, v_packed_da…324 …if (error_ == "") if (v_packed_data_64 !== v_packed_data_64_ref) error_ = "integer_vector_type log…
33 125 | v_packed_data_64 = {<<16{logic_in}};67 … ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64…69 135 | {<<16{logic_out}} = v_packed_data_64;