Searched refs:v_packed_data_64_ref (Results 1 – 1 of 1) sorted by relevance
| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_stream_integer_type.v | 34 logic [63:0] v_packed_data_64_ref; register
231 …$display("v_packed_data_64=%0h, v_packed_data_64_ref=%0h", v_packed_data_64, v_packed_data_64_ref);
262 … %s v_packed_data_64=%0h, v_packed_data_64_ref=%0h", name, v_packed_data_64, v_packed_data_64_ref);
287 v_packed_data_64_ref = {logic_in[3], logic_in[2], logic_in[1], logic_in[0]};
324 …if (error_ == "") if (v_packed_data_64 !== v_packed_data_64_ref) error_ = "integer_vector_type log…
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