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Searched refs:val_cfg0 (Results 1 – 25 of 119) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c654 u32 val_cfg0, val_cfg1; in frac_pll_init() local
666 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
679 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
680 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
683 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
684 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()
695 u32 val_cfg0, val_cfg1, val_cfg2, val; in sscg_pll_init() local
708 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
723 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
751 writel(val_cfg0 | bypass2_mask, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c654 u32 val_cfg0, val_cfg1; in frac_pll_init() local
666 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
679 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
680 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
683 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
684 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()
695 u32 val_cfg0, val_cfg1, val_cfg2, val; in sscg_pll_init() local
708 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
723 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
751 writel(val_cfg0 | bypass2_mask, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c654 u32 val_cfg0, val_cfg1; in frac_pll_init() local
666 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
679 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
680 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
683 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
684 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()
695 u32 val_cfg0, val_cfg1, val_cfg2, val; in sscg_pll_init() local
708 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
723 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
751 writel(val_cfg0 | bypass2_mask, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c654 u32 val_cfg0, val_cfg1; in frac_pll_init() local
666 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
679 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
680 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
683 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
684 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()
695 u32 val_cfg0, val_cfg1, val_cfg2, val; in sscg_pll_init() local
708 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
723 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
751 writel(val_cfg0 | bypass2_mask, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c654 u32 val_cfg0, val_cfg1; in frac_pll_init() local
666 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
679 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
680 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
683 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
684 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()
695 u32 val_cfg0, val_cfg1, val_cfg2, val; in sscg_pll_init() local
708 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
723 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
751 writel(val_cfg0 | bypass2_mask, pll_cfg1); in sscg_pll_init()
[all …]
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c218 u32 val_cfg0; in clock_init() local
227 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
228 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
233 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
235 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
236 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
241 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c398 u32 val_cfg0; in clock_init() local
407 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
415 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
416 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
421 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()

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