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Searched refs:verilog_state (Results 1 – 1 of 1) sorted by relevance

/dports/cad/electric/electric-7.00/src/sim/
H A Dsim.cpp4120 INTBIG itemHit, i, verilog_state, libcount, oldplease; in sim_verilogdlog() local
4150 if (var != NOVARIABLE) verilog_state = var->addr; else verilog_state = 0; in sim_verilogdlog()
4151 if ((verilog_state&VERILOGUSEASSIGN) != 0) DiaSetControl(dia, DVEO_USEASSIGN, 1); in sim_verilogdlog()
4152 if ((verilog_state&VERILOGUSETRIREG) != 0) DiaSetControl(dia, DVEO_USETRIREG, 1); in sim_verilogdlog()
4277 if (i != verilog_state) in sim_verilogdlog()