Searched refs:vert_timing (Results 1 – 7 of 7) sorted by relevance
78 (config->vert_timing[item] << 16), reg); in write_pair()293 config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; in tegra_decode_panel()294 config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; in tegra_decode_panel()295 config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back; in tegra_decode_panel()296 config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - in tegra_decode_panel()297 config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC]; in tegra_decode_panel()298 debug_timing("vert", config->vert_timing); in tegra_decode_panel()
67 uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ member
551 const uint16_t *vert_timing; in radeon_legacy_tv_mode_set() local733 vert_timing = vert_timing_NTSC; in radeon_legacy_tv_mode_set()736 vert_timing = vert_timing_PAL; in radeon_legacy_tv_mode_set()746 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) in radeon_legacy_tv_mode_set()
544 const uint16_t *vert_timing; in radeon_legacy_tv_mode_set() local720 vert_timing = vert_timing_NTSC; in radeon_legacy_tv_mode_set()723 vert_timing = vert_timing_PAL; in radeon_legacy_tv_mode_set()733 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) in radeon_legacy_tv_mode_set()
740 static const std::array<const UVIVBlankTimingRegister*, 2> vert_timing{{ in LogField() local751 m_VerticalTimingRegister.EQU, vert_timing[field_index]->PRB, in LogField()752 m_VerticalTimingRegister.ACV, vert_timing[field_index]->PSB, in LogField()