Searched refs:vita_time_reg (Results 1 – 4 of 4) sorted by relevance
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/timing/ |
| H A D | time_sender.v | 82 reg [63:0] vita_time_reg; register
86 vita_time_reg <= 0;
88 vita_time_reg <= vita_time;
110 {k,datain} <= {1'b0, vita_time_reg[63:56] };
115 {k,datain} <= {1'b0, vita_time_reg[55:48]};
120 {k,datain} <= {1'b0, vita_time_reg[47:40]};
125 {k,datain} <= {1'b0, vita_time_reg[39:32]};
130 {k,datain} <= {1'b0, vita_time_reg[31:24]};
135 {k,datain} <= {1'b0, vita_time_reg[23:16]};
140 {k,datain} <= {1'b0, vita_time_reg[15:8]};
[all …]
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | cvita_hdr_parser.v | 41 reg [63:0] hdr_reg, vita_time_reg; register
49 vita_time_reg <= 64'd0;
61 vita_time_reg <= o_tdata;
74 assign hdr_vita_time = (vita_time_stb | (REGISTER == 0)) ? o_tdata : vita_time_reg;
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | settings_fifo_ctrl.v | 276 reg [63:0] vita_time_reg; register
278 vita_time_reg <= vita_time;
283 .time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/ |
| H A D | wave.do | 41 add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_reg
|