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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Dprocessor.cc863 reg_t vsdeleg, hsdeleg; in take_trap() local
868vsdeleg = (curr_virt && state.prv <= PRV_S) ? (state.mideleg->read() & state.hideleg->read()) : 0; in take_trap()
872vsdeleg = (curr_virt && state.prv <= PRV_S) ? (state.medeleg->read() & state.hedeleg->read()) : 0; in take_trap()
875 if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { in take_trap()