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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
106 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll58 ; LE-NEXT: vslh 2, 2, 4
114 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
101 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
101 ; BE-NEXT: vslh 2, 2, 3
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
101 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
106 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
106 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
101 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
106 ; BE-NEXT: vslh 2, 2, 3
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
106 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll58 ; LE-NEXT: vslh 2, 2, 4
114 ; BE-NEXT: vslh 2, 2, 3
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll104 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
113 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
123 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
135 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
146 ; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
158 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
170 ; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
179 ; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
H A Dpr25080.ll50 ; LE-NEXT: vslh 2, 2, 4
101 ; BE-NEXT: vslh 2, 2, 3

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