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Searched refs:warn_sens_entire_arr (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/
H A Dcompiler.h102 extern bool warn_sens_entire_arr;
H A Dmain.cc167 bool warn_sens_entire_arr = false; variable
746 warn_sens_entire_arr = true; in read_iconfig_file()
H A Dnet_nex_input.cc217 if (!always_sens && warn_sens_entire_arr) { in nex_input_base()