| /dports/cad/alliance/alliance/src/loon/src/ |
| H A D | lon_normalize_register.c | 136 chain_list *setup=NULL, *not_stable=NULL, *wen=NULL; in loc_format_register() local
181 wen=biabl->CNDABL; in loc_format_register()
183 if (!ABL_CDR(wen)) { /* AND -> no wen */ in loc_format_register()
184 freechain(wen); in loc_format_register()
187 if (!ABL_CDR(ABL_CDR(wen))) { /* AND a -> wen = a */ in loc_format_register()
188 abl=ABL_CADR(wen); /* AND a b -> wen = a AND b */ in loc_format_register()
189 freechain(wen); in loc_format_register()
190 wen=abl; in loc_format_register()
192 abl= createablbinexpr(ABL_AND, createablnotexpr(wen), in loc_format_register()
194 biabl->VALABL= createablbinexpr(ABL_AND, dupablexpr(wen), in loc_format_register()
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| /dports/misc/urbit/urbit-urbit-0.6.0/vere/ |
| H A D | behn.c | 67 u3_noun wen = u3v_keep(u3nt(u3_blip, c3__behn, u3_nul)); in u3_behn_io_poll() local
69 if ( (u3_nul != wen) && in u3_behn_io_poll()
70 (c3y == u3du(wen)) && in u3_behn_io_poll()
71 (c3y == u3ud(u3t(wen))) ) in u3_behn_io_poll()
73 c3_d gap_d = u3_time_gap_ms(u3k(u3A->now), u3k(u3t(wen))); in u3_behn_io_poll()
94 u3z(wen); in u3_behn_io_poll()
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| H A D | time.c | 148 u3_time_gap_ms(u3_noun now, u3_noun wen) in u3_time_gap_ms() argument
150 if ( c3n == u3ka_gth(u3k(wen), u3k(now)) ) { in u3_time_gap_ms()
151 u3z(wen); u3z(now); in u3_time_gap_ms()
155 u3_noun dif = u3ka_sub(wen, now); in u3_time_gap_ms()
167 u3_time_gap_double(u3_noun now, u3_noun wen) in u3_time_gap_double() argument
174 u3r_mp(wen_mp, wen); in u3_time_gap_double()
179 u3z(wen); in u3_time_gap_double()
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/ |
| H A D | ssram.v | 4 module ssram(clock,addr,data,wen,ce);
11 input wen; port
22 read_d1 <= #1 ce & ~wen;
23 write_d1 <= #1 ce & wen;
35 if(~ce & (write_d2 | write_d1 | wen))
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/memmux01/ |
| H A D | tb_memmux03.vhdl | 9 signal wen : std_logic; signal
18 wen => wen,
37 wen <= '0';
47 wen <= '1';
51 wen <= '0';
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| H A D | tb_memmux02.vhdl | 9 signal wen : std_logic; signal
18 wen => wen,
37 wen <= '0';
47 wen <= '1';
51 wen <= '0';
|
| H A D | tb_memmux01.vhdl | 9 signal wen : std_logic; signal
18 wen => wen,
36 wen <= '0';
43 wen <= '1';
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/mem2d01/ |
| H A D | tb_memmux04.vhdl | 9 signal wen : std_logic; signal
19 wen => wen,
39 wen <= '1';
44 wen <= '1';
54 wen <= '1';
69 wen <= '0';
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/ |
| H A D | generic_fifo.v | 44 wen,
77 input wen; port
107 .wen (wen),
137 .wen (mem_wen),
162 .wen (mem_wen),
188 .wen (mem_wen),
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| H A D | generic_mem_medium.v | 43 wen,
70 input wen; port
111 if (wen) begin
119 always @(wen, waddr, wdata)
121 if (wen) begin
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| H A D | generic_mem_small.v | 44 wen,
71 input wen; port
112 if (wen) begin
120 always @(wen, waddr, wdata)
122 if (wen) begin
|
| /dports/devel/nextpnr/nextpnr-48cd407/ice40/benchmark/ |
| H A D | picosoc.v | 194 .wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
205 input clk, wen, port
216 if (wen) regs[waddr[4:0]] <= wdata;
226 input [3:0] wen, port
235 if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
236 if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
237 if (wen[2]) mem[addr][23:16] <= wdata[23:16];
238 if (wen[3]) mem[addr][31:24] <= wdata[31:24];
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/mem01/ |
| H A D | tb_sram05.vhdl | 12 signal wen : std_logic; signal
18 wen_i => wen);
34 wen <= '1';
52 wen <= '0';
57 wen <= '1';
74 wen <= '0';
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| H A D | tb_sram01.vhdl | 11 signal wen : std_logic; signal
16 wen_i => wen);
29 wen <= '1';
37 wen <= '0';
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| H A D | tb_sram03.vhdl | 11 signal wen : std_logic; signal
16 wen_i => wen);
29 wen <= '1';
44 wen <= '0';
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| H A D | tb_sram02.vhdl | 11 signal wen : std_logic; signal
16 wen_i => wen);
29 wen <= '1';
41 wen <= '0';
|
| /dports/cad/py-pymtl/pymtl3-3.1.6/pymtl3/stdlib/stream/ |
| H A D | queues.py | 70 s.wen = InPort()
79 m.wen[0] //= s.wen
101 s.wen = OutPort()
117 s.wen //= s.recv_xfer
177 s.ctrl.wen //= s.dpath.wen
268 s.wen = OutPort()
343 s.ctrl.wen //= s.dpath.wen
421 s.wen = InPort()
430 m.wen[0] //= s.wen
460 s.wen = OutPort()
[all …]
|
| /dports/cad/py-pymtl/pymtl3-3.1.6/pymtl3/stdlib/queues/ |
| H A D | queues.py | 29 s.wen = InPort()
38 m.wen[0] //= s.wen
63 s.wen = OutPort()
79 connect( s.wen, s.enq_xfer )
138 connect( s.ctrl.wen, s.dpath.wen )
182 s.wen = OutPort( Bits1 )
198 connect( s.wen, s.enq_xfer )
257 connect( s.ctrl.wen, s.dpath.wen )
289 s.wen = InPort( Bits1 )
298 m.wen[0] //= s.wen
[all …]
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_reloop_cam.v | 25 wire wen = crc[34]; net
51 .wen (wen),
108 input wen, port
129 wen_d1r <= wen;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | dpram.v | 24 module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
32 input wen; port
41 if(wen)
|
| /dports/devel/radare2/radare2-5.1.1/test/db/cmd/ |
| H A D | write | 1 NAME=wen 3
5 wen 3
19 o .tmp/ls-wen
21 wen 3
25 wen 3
27 rm .tmp/ls-wen
42 wen 3
382 NAME=wen
387 wen 2 @ 1
388 wen 1 @ 6
[all …]
|
| /dports/cad/cascade-compiler/cascade-f4f7ae8bd1dd379790c0e58c286df90b8d1cdcde/share/cascade/test/regression/simple/ |
| H A D | mem_2.v | 9 input wire wen, port
18 if (wen)
27 .wen(1),
|
| /dports/misc/tvm/incubator-tvm-0.6.1/vta/apps/tsim_example/hardware/verilog/src/ |
| H A D | RegFile.v | 108 logic wen = (state_r == IDLE)? host_req_valid & host_req_opcode & i*4 == host_req_addr : 1'b0; register
117 end else if (wen) begin
129 end else if (wen) begin
139 end else if (wen) begin
|
| /dports/misc/py-tvm/incubator-tvm-0.6.1/vta/apps/tsim_example/hardware/verilog/src/ |
| H A D | RegFile.v | 108 logic wen = (state_r == IDLE)? host_req_valid & host_req_opcode & i*4 == host_req_addr : 1'b0; register
117 end else if (wen) begin
129 end else if (wen) begin
139 end else if (wen) begin
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| /dports/cad/alliance/alliance/src/cells/src/dp_sxlib/ |
| H A D | dp_sff_x4_buf.vbe | 4 wen : in BIT;
23 wenx <= wen;
24 nwenx <= not wen;
|