| /dports/emulators/x48/x48-0.6.4_1/src/ |
| H A D | serial.c | 95 static char *wire_name = (char *)0; variable
109 if (wire_name) free(wire_name); in update_connection_display()
110 wire_name = (char *)0; in update_connection_display()
117 ShowConnections(wire_name, ir_name); in update_connection_display()
145 wire_name = strdup(tty_dev_name); in serial_init()
167 wire_name = strdup(p); in serial_init()
184 wire_name = strdup(tty_dev_name); in serial_init()
202 wire_name = strdup(tty_dev_name); in serial_init()
222 wire_name = strdup(tty_dev_name); in serial_init()
254 wire_name = strdup(tty_dev_name); in serial_init()
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/blif/ |
| H A D | blifparse.cc | 95 auto blif_wire = [&](const std::string &wire_name) -> Wire* in parse_blif()
97 if (wire_name[0] == '$') in parse_blif()
99 for (int i = 0; i+1 < GetSize(wire_name); i++) in parse_blif()
101 if (wire_name[i] != '$') in parse_blif()
105 while (i+len+1 < GetSize(wire_name) && '0' <= wire_name[i+len+1] && wire_name[i+len+1] <= '9') in parse_blif()
109 string num_str = wire_name.substr(i+1, len); in parse_blif()
116 IdString wire_id = RTLIL::escape_id(wire_name); in parse_blif()
259 RTLIL::IdString wire_name(stringf("\\%s", p)); in parse_blif() local
260 RTLIL::Wire *wire = module->wire(wire_name); in parse_blif()
262 wire = module->addWire(wire_name); in parse_blif()
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| /dports/devel/py-botocore/botocore-1.21.61/tests/unit/ |
| H A D | test_monitoring.py | 87 self.wire_name = 'MyOperation'
89 self.operation_model.wire_name = self.wire_name
156 operation=self.wire_name,
180 operation=self.wire_name,
206 operation=self.wire_name,
232 operation=self.wire_name,
256 operation=self.wire_name,
306 operation=self.wire_name,
336 operation=self.wire_name,
356 operation=self.wire_name,
[all …]
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| H A D | test_model.py | 200 self.assertEqual(operation.wire_name, 'OperationName')
212 self.assertEqual(operation.wire_name, 'OperationName')
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| /dports/dns/validns/validns-0.8/ |
| H A D | nsec3checks.c | 37 struct binary_data wire_name = name2wire_name(name); in name2hash() local
43 if (wire_name.length < 0) in name2hash()
52 EVP_DigestUpdate(ctx, wire_name.data, wire_name.length); in name2hash()
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| /dports/devel/trellis/prjtrellis-5eb0ad87/libtrellis/src/ |
| H A D | RoutingGraph.cpp | 141 …tingGraph::add_bel_input(RoutingBel &bel, ident_t pin, int wire_x, int wire_y, ident_t wire_name) { in add_bel_input() argument
143 wireId.id = wire_name; in add_bel_input()
153 …ingGraph::add_bel_output(RoutingBel &bel, ident_t pin, int wire_x, int wire_y, ident_t wire_name) { in add_bel_output() argument
155 wireId.id = wire_name; in add_bel_output()
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| /dports/cad/iverilog/verilog-11.0/tgt-pcb/ |
| H A D | scope.cc | 41 static string wire_name(ivl_signal_t sig);
109 nex_data->name = wire_name(sig); in sheet_box()
225 static string wire_name(ivl_signal_t sig) in wire_name() function
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| /dports/x11/libXrandr/libXrandr-1.5.2/src/ |
| H A D | XrrScreen.c | 53 char *wire_names, *wire_name; in doGetScreenResources() local
184 wire_name = wire_names; in doGetScreenResources()
195 memcpy (names, wire_name, xrsr->modes[i].nameLength); in doGetScreenResources()
198 wire_name += xrsr->modes[i].nameLength; in doGetScreenResources()
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| /dports/net/wireshark-lite/wireshark-3.6.1/epan/dissectors/ |
| H A D | packet-riemann.c | 161 const char *wire_name; in riemann_verify_wire_format() local
165 wire_name = "integer"; in riemann_verify_wire_format()
168 wire_name = "bytes/string"; in riemann_verify_wire_format()
171 wire_name = "float"; in riemann_verify_wire_format()
174 wire_name = "double"; in riemann_verify_wire_format()
177 wire_name = "unknown (check packet-riemann.c)"; in riemann_verify_wire_format()
182 field_name, (int)field_number, wire_name, expected, actual); in riemann_verify_wire_format()
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| /dports/net/wireshark/wireshark-3.6.1/epan/dissectors/ |
| H A D | packet-riemann.c | 161 const char *wire_name; in riemann_verify_wire_format() local
165 wire_name = "integer"; in riemann_verify_wire_format()
168 wire_name = "bytes/string"; in riemann_verify_wire_format()
171 wire_name = "float"; in riemann_verify_wire_format()
174 wire_name = "double"; in riemann_verify_wire_format()
177 wire_name = "unknown (check packet-riemann.c)"; in riemann_verify_wire_format()
182 field_name, (int)field_number, wire_name, expected, actual); in riemann_verify_wire_format()
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| /dports/net/tshark-lite/wireshark-3.6.1/epan/dissectors/ |
| H A D | packet-riemann.c | 161 const char *wire_name; in riemann_verify_wire_format() local
165 wire_name = "integer"; in riemann_verify_wire_format()
168 wire_name = "bytes/string"; in riemann_verify_wire_format()
171 wire_name = "float"; in riemann_verify_wire_format()
174 wire_name = "double"; in riemann_verify_wire_format()
177 wire_name = "unknown (check packet-riemann.c)"; in riemann_verify_wire_format()
182 field_name, (int)field_number, wire_name, expected, actual); in riemann_verify_wire_format()
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| /dports/net/tshark/wireshark-3.6.1/epan/dissectors/ |
| H A D | packet-riemann.c | 161 const char *wire_name;
165 wire_name = "integer";
168 wire_name = "bytes/string";
171 wire_name = "float";
174 wire_name = "double";
177 wire_name = "unknown (check packet-riemann.c)";
182 field_name, (int)field_number, wire_name, expected, actual);
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| /dports/devel/trellis/prjtrellis-5eb0ad87/libtrellis/include/ |
| H A D | RoutingGraph.hpp | 158 void add_bel_input(RoutingBel &bel, ident_t pin, int wire_x, int wire_y, ident_t wire_name);
159 void add_bel_output(RoutingBel &bel, ident_t pin, int wire_x, int wire_y, ident_t wire_name);
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| /dports/cad/lepton-eda/lepton-eda-1.9.17/utils/netlist/docs/ |
| H A D | README.sysc | 11 1.- Only transaction based wires are considered (wire_name<user_type>).
|
| /dports/cad/geda/geda-gaf-1.8.2/gnetlist/docs/ |
| H A D | README.sysc | 11 1.- Only transaction based wires are considered (wire_name<user_type>).
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/aiger/ |
| H A D | aigerparse.cc | 343 RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : "")); in createWireIfNotExists() local
344 RTLIL::Wire *wire = module->wire(wire_name); in createWireIfNotExists()
346 log_debug2("Creating %s\n", wire_name.c_str()); in createWireIfNotExists()
347 wire = module->addWire(wire_name); in createWireIfNotExists()
361 log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); in createWireIfNotExists()
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| /dports/net/google-cloud-sdk/google-cloud-sdk/lib/third_party/botocore/ |
| H A D | model.py | 442 return self.wire_name
445 def wire_name(self): member in OperationModel
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| H A D | monitoring.py | 99 operation=model.wire_name,
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| /dports/devel/py-botocore/botocore-1.21.61/botocore/ |
| H A D | model.py | 463 return self.wire_name
466 def wire_name(self): member in OperationModel
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| H A D | monitoring.py | 99 operation=model.wire_name,
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/ast/ |
| H A D | genrtlil.cc | 453 std::string wire_name; in new_temp_signal() local
455 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++, in new_temp_signal()
458 wire_name += stringf("$%d", autoidx++); in new_temp_signal()
459 } while (current_module->wires_.count(wire_name) > 0); in new_temp_signal()
461 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width); in new_temp_signal()
1955 RTLIL::IdString wire_name = NEW_ID; in genRTLIL() local
1956 RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig)); in genRTLIL()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/techmap/ |
| H A D | techmap.cc | 55 IdString wire_name = chunk.wire->name; in apply_prefix() local
56 apply_prefix(prefix, wire_name); in apply_prefix()
57 log_assert(module->wire(wire_name) != nullptr); in apply_prefix()
58 chunk.wire = module->wire(wire_name); in apply_prefix()
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| /dports/cad/yosys/yosys-yosys-0.12/kernel/ |
| H A D | celltypes.h | 67 for (RTLIL::IdString wire_name : module->ports) { in setup_module() local
68 RTLIL::Wire *wire = module->wire(wire_name); in setup_module()
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/verific/ |
| H A D | verific.cc | 1249 …RTLIL::IdString wire_name = module->uniquify(mode_names || net->IsUserDeclared() ? RTLIL::escape_i… in import_netlist() local
1252 log(" importing net %s as %s.\n", net->Name(), log_id(wire_name)); in import_netlist()
1254 RTLIL::Wire *wire = module->addWire(wire_name); in import_netlist()
1273 …RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escap… in import_netlist() local
1276 log(" importing netbus %s as %s.\n", netbus->Name(), log_id(wire_name)); in import_netlist()
1278 RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size()); in import_netlist()
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/verilog/ |
| H A D | verilog_parser.y | 1132 } wire_name |
1144 } wire_name;
1930 wire_name {
1972 wire_name '=' expr {
1999 wire_name:
|