Searched refs:wren_a (Results 1 – 8 of 8) sorted by relevance
/dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/common/ |
H A D | m9k_bb.v | 20 module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b, 54 input wren_a; port
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H A D | brams_map_m9k.v | 73 .wren_a(B1EN),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
H A D | fifo_2k.v | 1266 .ena0(wren_a), 1325 .ena0(wren_a), 1384 .ena0(wren_a), 1443 .ena0(wren_a), 1502 .ena0(wren_a), 1561 .ena0(wren_a), 1620 .ena0(wren_a), 1679 .ena0(wren_a), 1738 .ena0(wren_a), 1797 .ena0(wren_a), [all …]
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H A D | fifo_4k.v | 1358 .ena0(wren_a), 1417 .ena0(wren_a), 1476 .ena0(wren_a), 1535 .ena0(wren_a), 1594 .ena0(wren_a), 1653 .ena0(wren_a), 1712 .ena0(wren_a), 1771 .ena0(wren_a), 1830 .ena0(wren_a), 1889 .ena0(wren_a), [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/ |
H A D | idt71v65603s150.v | 94 reg wren_a, wren_b; register 188 if ( ~cen_ & ~adv_ld_ ) wren_a <= #regdelay (cs & ~r_w_); 189 if ( ~cen_ ) wren_b <= #regdelay wren_a;
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/dports/cad/yosys/yosys-yosys-0.12/techlibs/intel_alm/common/ |
H A D | bram_m20k_map.v | 24 .wren_a(A1EN),
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H A D | megafunction_bb.v | 486 module altsyncram(clock0, clock1, address_a, data_a, rden_a, wren_a, byteena_a, q_a, addressstall_a… 514 input wren_a; port
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1243/ |
H A D | DSPn.vhdl | 116 wren_a : in STD_LOGIC := '0'; port in DSPn.rtl.dp16k_wrapper_8bit 491 wren_a => DATA_RAM_WE, 504 wren_a => DATA_RAM_WE,
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