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Searched refs:wren_a (Results 1 – 8 of 8) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/common/
H A Dm9k_bb.v20 module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
54 input wren_a; port
H A Dbrams_map_m9k.v73 .wren_a(B1EN),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/
H A Dfifo_2k.v1266 .ena0(wren_a),
1325 .ena0(wren_a),
1384 .ena0(wren_a),
1443 .ena0(wren_a),
1502 .ena0(wren_a),
1561 .ena0(wren_a),
1620 .ena0(wren_a),
1679 .ena0(wren_a),
1738 .ena0(wren_a),
1797 .ena0(wren_a),
[all …]
H A Dfifo_4k.v1358 .ena0(wren_a),
1417 .ena0(wren_a),
1476 .ena0(wren_a),
1535 .ena0(wren_a),
1594 .ena0(wren_a),
1653 .ena0(wren_a),
1712 .ena0(wren_a),
1771 .ena0(wren_a),
1830 .ena0(wren_a),
1889 .ena0(wren_a),
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/
H A Didt71v65603s150.v94 reg wren_a, wren_b; register
188 if ( ~cen_ & ~adv_ld_ ) wren_a <= #regdelay (cs & ~r_w_);
189 if ( ~cen_ ) wren_b <= #regdelay wren_a;
/dports/cad/yosys/yosys-yosys-0.12/techlibs/intel_alm/common/
H A Dbram_m20k_map.v24 .wren_a(A1EN),
H A Dmegafunction_bb.v486 module altsyncram(clock0, clock1, address_a, data_a, rden_a, wren_a, byteena_a, q_a, addressstall_a…
514 input wren_a; port
/dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1243/
H A DDSPn.vhdl116 wren_a : in STD_LOGIC := '0'; port in DSPn.rtl.dp16k_wrapper_8bit
491 wren_a => DATA_RAM_WE,
504 wren_a => DATA_RAM_WE,