Home
last modified time | relevance | path

Searched refs:xilinx_cell_lut4 (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-fpga/
H A Dd-virtex.c74 edif_cell_t cell_lut4 = xilinx_cell_lut4(xlib); in virtex_or_wide()
383 lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib)); in virtex_eq()
417 lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib)); in virtex_eq()
531 lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib)); in virtex_ge()
H A Dxilinx.h57 extern edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib);
H A Dxilinx.c160 edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib) in xilinx_cell_lut4() function
564 lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib)); in lut_logic()
862 lut = xilinx_cell_lut4(xlib); in xilinx_shiftl()