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Searched refs:AR_PHY_PLL_CTL_44 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211phy.h45 #define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */ macro
H A Dar5211_attach.c256 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); in ar5211Attach()
H A Dar5211_reset.c607 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); in ar5211ChipReset()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212phy.h142 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */ macro
H A Dar5212_reset.c908 phyPLL = AR_PHY_PLL_CTL_44; in ar5212ChipReset()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5312/
H A Dar5312_reset.c681 phyPLL = AR_PHY_PLL_CTL_44; in ar5312ChipReset()