Searched refs:AR_PHY_PLL_CTL_44 (Results 1 – 6 of 6) sorted by relevance
45 #define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */ macro
256 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); in ar5211Attach()
607 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); in ar5211ChipReset()
142 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */ macro
908 phyPLL = AR_PHY_PLL_CTL_44; in ar5212ChipReset()
681 phyPLL = AR_PHY_PLL_CTL_44; in ar5312ChipReset()