Home
last modified time | relevance | path

Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dcikd.h1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
H A Dcik.c6916 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7098 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7208 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c4400 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
4406 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6892 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
7108 WREG32_FIELD_OFFSET(CP_ME1_PIPE0_INT_CNTL, in gfx_v8_0_kiq_set_interrupt_state()