Searched refs:DP_TP_CTL (Results 1 – 3 of 3) sorted by relevance
975 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()1038 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()1042 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()1055 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()2280 val = I915_READ(DP_TP_CTL(port)); in intel_disable_ddi_buf()2283 I915_WRITE(DP_TP_CTL(port), val); in intel_disable_ddi_buf()2500 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()2503 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()2504 POSTING_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()2519 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()[all …]
2782 uint32_t temp = I915_READ(DP_TP_CTL(port)); in _intel_dp_set_link_train()2805 I915_WRITE(DP_TP_CTL(port), temp); in _intel_dp_set_link_train()3578 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()3581 I915_WRITE(DP_TP_CTL(port), val); in intel_dp_set_idle_link_train()
8332 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) macro