1 /*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/dev/ena/ena.h 325592 2017-11-09 13:36:42Z mw $
31 *
32 */
33
34 #ifndef ENA_H
35 #define ENA_H
36
37 #include <sys/types.h>
38 #include <sys/_timeval.h>
39
40 #include "ena-com/ena_com.h"
41 #include "ena-com/ena_eth_com.h"
42
43 #define DRV_MODULE_VER_MAJOR 0
44 #define DRV_MODULE_VER_MINOR 8
45 #define DRV_MODULE_VER_SUBMINOR 0
46
47 #define DRV_MODULE_NAME "ena"
48
49 #ifndef DRV_MODULE_VERSION
50 #define DRV_MODULE_VERSION \
51 __XSTRING(DRV_MODULE_VER_MAJOR) "." \
52 __XSTRING(DRV_MODULE_VER_MINOR) "." \
53 __XSTRING(DRV_MODULE_VER_SUBMINOR)
54 #endif
55 #define DEVICE_NAME "Elastic Network Adapter (ENA)"
56 #define DEVICE_DESC "ENA adapter"
57
58 #ifdef __DragonFly__
59 #define SBT_1S ((__int64_t)1 << 32) /* XXX this should not be needed */
60 typedef struct ifnet * if_t;
61 #endif
62
63 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
64 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
65
66 /* 1 for AENQ + ADMIN */
67 #define ENA_ADMIN_MSIX_VEC 1
68 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
69
70 #define ENA_REG_BAR 0
71 #define ENA_MEM_BAR 2
72
73 #define ENA_BUS_DMA_SEGS 32
74
75 #define ENA_DEFAULT_RING_SIZE 1024
76
77 #define ENA_RX_REFILL_THRESH_DIVIDER 8
78
79 #define ENA_IRQNAME_SIZE 40
80
81 #define ENA_PKT_MAX_BUFS 19
82
83 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
84 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
85
86 #define ENA_HASH_KEY_SIZE 40
87
88 #define ENA_MAX_FRAME_LEN 10000
89 #define ENA_MIN_FRAME_LEN 60
90
91 #define ENA_TX_CLEANUP_THRESHOLD 128
92
93 #define DB_THRESHOLD 64
94
95 #define TX_COMMIT 32
96 /*
97 * TX budget for cleaning. It should be half of the RX budget to reduce amount
98 * of TCP retransmissions.
99 */
100 #define TX_BUDGET 128
101 /* RX cleanup budget. -1 stands for infinity. */
102 #define RX_BUDGET 256
103 /*
104 * How many times we can repeat cleanup in the io irq handling routine if the
105 * RX or TX budget was depleted.
106 */
107 #define CLEAN_BUDGET 8
108
109 #define RX_IRQ_INTERVAL 20
110 #define TX_IRQ_INTERVAL 50
111
112 #define ENA_MIN_MTU 128
113
114 #define ENA_TSO_MAXSIZE 65536
115
116 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
117
118 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
119
120 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
121
122 #define ENA_IO_TXQ_IDX(q) (2 * (q))
123 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
124
125 #define ENA_MGMNT_IRQ_IDX 0
126 #define ENA_IO_IRQ_FIRST_IDX 1
127 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
128
129 /*
130 * ENA device should send keep alive msg every 1 sec.
131 * We wait for 6 sec just to be on the safe side.
132 */
133 #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
134
135 /* Time in jiffies before concluding the transmitter is hung. */
136 #define DEFAULT_TX_CMP_TO (SBT_1S * 5)
137
138 /* Number of queues to check for missing queues per timer tick */
139 #define DEFAULT_TX_MONITORED_QUEUES (4)
140
141 /* Max number of timeouted packets before device reset */
142 #define DEFAULT_TX_CMP_THRESHOLD (128)
143
144 /*
145 * Supported PCI vendor and devices IDs
146 */
147 #define PCI_VENDOR_ID_AMAZON 0x1d0f
148
149 #define PCI_DEV_ID_ENA_PF 0x0ec2
150 #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2
151 #define PCI_DEV_ID_ENA_VF 0xec20
152 #define PCI_DEV_ID_ENA_LLQ_VF 0xec21
153
154 struct msix_entry {
155 int entry;
156 int vector;
157 };
158
159 typedef struct _ena_vendor_info_t {
160 unsigned int vendor_id;
161 unsigned int device_id;
162 unsigned int index;
163 } ena_vendor_info_t;
164
165 struct ena_irq {
166 /* Interrupt resources */
167 struct resource *res;
168 driver_intr_t *handler;
169 void *data;
170 void *cookie;
171 unsigned int vector;
172 bool requested;
173 int cpu;
174 char name[ENA_IRQNAME_SIZE];
175 };
176
177 struct ena_que {
178 struct ena_adapter *adapter;
179 struct ena_ring *tx_ring;
180 struct ena_ring *rx_ring;
181 uint32_t id;
182 int cpu;
183 };
184
185 struct ena_tx_buffer {
186 struct mbuf *mbuf;
187 /* # of ena desc for this specific mbuf
188 * (includes data desc and metadata desc) */
189 unsigned int tx_descs;
190 /* # of buffers used by this mbuf */
191 unsigned int num_of_bufs;
192 bus_dmamap_t map;
193
194 /* Used to detect missing tx packets */
195 struct timeval timestamp;
196 bool print_once;
197
198 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
199 } __cachealign;
200
201 struct ena_rx_buffer {
202 struct mbuf *mbuf;
203 bus_dmamap_t map;
204 struct ena_com_buf ena_buf;
205 } __cachealign;
206
207 #if 0 /* XXX swildner counters */
208 struct ena_stats_tx {
209 counter_u64_t cnt;
210 counter_u64_t bytes;
211 counter_u64_t prepare_ctx_err;
212 counter_u64_t dma_mapping_err;
213 counter_u64_t doorbells;
214 counter_u64_t missing_tx_comp;
215 counter_u64_t bad_req_id;
216 counter_u64_t collapse;
217 counter_u64_t collapse_err;
218 };
219
220 struct ena_stats_rx {
221 counter_u64_t cnt;
222 counter_u64_t bytes;
223 counter_u64_t refil_partial;
224 counter_u64_t bad_csum;
225 counter_u64_t mjum_alloc_fail;
226 counter_u64_t mbuf_alloc_fail;
227 counter_u64_t dma_mapping_err;
228 counter_u64_t bad_desc_num;
229 counter_u64_t bad_req_id;
230 counter_u64_t empty_rx_ring;
231 };
232 #endif
233
234 struct ena_ring {
235 /* Holds the empty requests for TX/RX out of order completions */
236 union {
237 uint16_t *free_tx_ids;
238 uint16_t *free_rx_ids;
239 };
240 struct ena_com_dev *ena_dev;
241 struct ena_adapter *adapter;
242 struct ena_com_io_cq *ena_com_io_cq;
243 struct ena_com_io_sq *ena_com_io_sq;
244
245 uint16_t qid;
246
247 /* Determines if device will use LLQ or normal mode for TX */
248 enum ena_admin_placement_policy_type tx_mem_queue_type;
249 /* The maximum length the driver can push to the device (For LLQ) */
250 uint8_t tx_max_header_size;
251
252 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
253
254 /*
255 * Fields used for Adaptive Interrupt Modulation - to be implemented in
256 * the future releases
257 */
258 uint32_t smoothed_interval;
259 enum ena_intr_moder_level moder_tbl_idx;
260
261 struct ena_que *que;
262 #if 0 /* XXX LRO */
263 struct lro_ctrl lro;
264 #endif
265
266 uint16_t next_to_use;
267 uint16_t next_to_clean;
268
269 union {
270 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
271 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
272 };
273 int ring_size; /* number of tx/rx_buffer_info's entries */
274
275 struct lock ring_lock;
276 char lock_name[16];
277
278 union {
279 struct {
280 struct task cmpl_task;
281 struct taskqueue *cmpl_tq;
282 };
283 };
284
285 #if 0 /* XXX swildner counters */
286 union {
287 struct ena_stats_tx tx_stats;
288 struct ena_stats_rx rx_stats;
289 };
290 #endif
291
292 int empty_rx_queue;
293 } __cachealign;
294
295 #if 0 /* XXX swildner counters */
296 struct ena_stats_dev {
297 counter_u64_t wd_expired;
298 counter_u64_t interface_up;
299 counter_u64_t interface_down;
300 counter_u64_t admin_q_pause;
301 };
302
303 struct ena_hw_stats {
304 counter_u64_t rx_packets;
305 counter_u64_t tx_packets;
306
307 counter_u64_t rx_bytes;
308 counter_u64_t tx_bytes;
309
310 counter_u64_t rx_drops;
311 };
312 #endif
313
314 /* Board specific private data structure */
315 struct ena_adapter {
316 struct ena_com_dev *ena_dev;
317
318 /* OS defined structs */
319 if_t ifp;
320 device_t pdev;
321 struct ifmedia media;
322
323 /* OS resources */
324 struct resource *memory;
325 struct resource *registers;
326
327 struct lock global_lock;
328 struct lock ioctl_lock;
329
330 /* MSI-X */
331 uint32_t msix_enabled;
332 struct msix_entry *msix_entries;
333 int msix_vecs;
334
335 /* DMA tags used throughout the driver adapter for Tx and Rx */
336 bus_dma_tag_t tx_buf_tag;
337 bus_dma_tag_t rx_buf_tag;
338 int dma_width;
339
340 uint32_t max_mtu;
341
342 uint16_t max_tx_sgl_size;
343 uint16_t max_rx_sgl_size;
344
345 uint32_t tx_offload_cap;
346
347 /* Tx fast path data */
348 int num_queues;
349
350 unsigned int tx_ring_size;
351 unsigned int rx_ring_size;
352
353 /* RSS*/
354 uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE];
355 bool rss_support;
356
357 uint8_t mac_addr[ETHER_ADDR_LEN];
358 /* mdio and phy*/
359
360 bool link_status;
361 bool trigger_reset;
362 bool up;
363 bool running;
364
365 /* Queue will represent one TX and one RX ring */
366 struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
367 __cachealign;
368
369 /* TX */
370 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
371 __cachealign;
372
373 /* RX */
374 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
375 __cachealign;
376
377 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
378
379 /* Timer service */
380 struct callout timer_service;
381 struct timeval keep_alive_timestamp;
382 uint32_t next_monitored_tx_qid;
383 struct task reset_task;
384 struct taskqueue *reset_tq;
385 int wd_active;
386 time_t keep_alive_timeout;
387 time_t missing_tx_timeout;
388 uint32_t missing_tx_max_queues;
389 uint32_t missing_tx_threshold;
390
391 #if 0 /* XXX swildner counters */
392 /* Statistics */
393 struct ena_stats_dev dev_stats;
394 struct ena_hw_stats hw_stats;
395 #endif
396
397 enum ena_regs_reset_reason_types reset_reason;
398 };
399
400 #define ENA_RING_MTX_LOCK(_ring) lockmgr(&(_ring)->ring_lock, LK_EXCLUSIVE)
401 #define ENA_RING_MTX_TRYLOCK(_ring) lockmgr_try(&(_ring)->ring_lock, LK_EXCLUSIVE)
402 #define ENA_RING_MTX_UNLOCK(_ring) lockmgr(&(_ring)->ring_lock, LK_RELEASE)
403
ena_mbuf_count(struct mbuf * mbuf)404 static inline int ena_mbuf_count(struct mbuf *mbuf)
405 {
406 int count = 1;
407
408 while ((mbuf = mbuf->m_next) != NULL)
409 ++count;
410
411 return count;
412 }
413
414 #endif /* !(ENA_H) */
415