/dragonfly/sys/dev/drm/amd/display/dc/dce/ |
H A D | dce_opp.h | 45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 90 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 91 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 92 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 93 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 98 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 107 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 108 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 109 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 110 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ [all …]
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H A D | dce_opp.c | 109 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 118 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 134 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation() 163 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() 168 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() 173 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() 235 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() 245 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither() 267 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither() 302 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither() [all …]
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
H A D | dcn10_opp.c | 53 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in opp1_set_truncation() 64 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither() 121 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
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H A D | dcn10_opp.h | 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 54 uint32_t FMT_BIT_DEPTH_CONTROL; \
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 525 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt() 528 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt() 529 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt() 537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt() 541 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt() 542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v10_0_program_fmt() 550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt() 551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt() 554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt() [all …]
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H A D | dce_v11_0.c | 551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt() 554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt() 555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt() 563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt() 567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt() 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v11_0_program_fmt() 576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt() 577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt() 580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt() [all …]
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/dragonfly/sys/dev/drm/radeon/ |
H A D | cikd.h | 987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
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H A D | evergreend.h | 1376 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
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H A D | r600d.h | 1245 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
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H A D | r600.c | 336 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
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H A D | evergreen.c | 1330 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
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H A D | cik.c | 8770 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
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