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Searched refs:GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h636 #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 macro
H A Dbif_5_0_sh_mask.h720 #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 macro
H A Dbif_5_1_sh_mask.h690 #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 macro