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Searched refs:GENMASK_ULL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_debugfs.c132 me = (*pos & GENMASK_ULL(33, 24)) >> 24; in amdgpu_debugfs_process_reg_op()
133 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; in amdgpu_debugfs_process_reg_op()
134 queue = (*pos & GENMASK_ULL(53, 44)) >> 44; in amdgpu_debugfs_process_reg_op()
629 offset = (*pos & GENMASK_ULL(6, 0)); in amdgpu_debugfs_wave_read()
630 se = (*pos & GENMASK_ULL(14, 7)) >> 7; in amdgpu_debugfs_wave_read()
631 sh = (*pos & GENMASK_ULL(22, 15)) >> 15; in amdgpu_debugfs_wave_read()
632 cu = (*pos & GENMASK_ULL(30, 23)) >> 23; in amdgpu_debugfs_wave_read()
633 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
702 se = (*pos & GENMASK_ULL(19, 12)) >> 12; in amdgpu_debugfs_gpr_read()
703 sh = (*pos & GENMASK_ULL(27, 20)) >> 20; in amdgpu_debugfs_gpr_read()
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/dragonfly/sys/dev/virtual/amazon/ena/ena-com/
H A Dena_eth_com.c489 GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); in ena_com_prepare_tx()
586 ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); in ena_com_add_single_rx_desc()
H A Dena_plat.h160 #define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) macro
H A Dena_com.c110 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { in ena_com_mem_addr_set()
/dragonfly/sys/dev/drm/include/linux/
H A Dbitops.h517 #define GENMASK_ULL(h, l) \ macro
/dragonfly/sys/dev/drm/i915/
H A Di915_gem_execbuffer.c269 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0); in gen8_noncanonical_addr()
2420 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */ in i915_gem_do_execbuffer()
H A Dintel_runtime_pm.c1022 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))