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Searched refs:GENMO_RD__VGA_HSYNC_POL__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7156 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 macro
H A Ddce_8_0_sh_mask.h10626 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_10_0_sh_mask.h11010 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_11_0_sh_mask.h10822 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_11_2_sh_mask.h12076 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_12_0_sh_mask.h2249 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h888 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro