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Searched refs:GFX_OP_PIPE_CONTROL (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_ringbuffer.c185 *cs++ = GFX_OP_PIPE_CONTROL(5); in intel_emit_post_sync_nonzero_flush()
197 *cs++ = GFX_OP_PIPE_CONTROL(5); in intel_emit_post_sync_nonzero_flush()
251 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_render_ring_flush()
269 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_render_ring_cs_stall_wa()
331 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_render_ring_flush()
727 *cs++ = GFX_OP_PIPE_CONTROL(6); in gen8_rcs_signal()
855 *cs++ = GFX_OP_PIPE_CONTROL(6); in gen8_render_emit_breadcrumb()
H A Dintel_ringbuffer.h859 batch[0] = GFX_OP_PIPE_CONTROL(6); in gen8_emit_pipe_control()
H A Di915_cmd_parser.c291 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
H A Dintel_lrc.c1835 *cs++ = GFX_OP_PIPE_CONTROL(6); in gen8_emit_breadcrumb_render()
H A Di915_reg.h624 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) macro