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Searched refs:MC_SEQ_MISC_TIMING_LP (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dbtcd.h149 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
H A Dbtc_dpm.c1864 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
2029 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in btc_initialize_mc_reg_table()
H A Dnid.h807 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
H A Dsid.h575 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
H A Dcikd.h700 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
H A Devergreend.h325 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
H A Dni_dpm.c2778 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2883 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ni_initialize_mc_reg_table()
H A Dcypress_dpm.c979 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
H A Dci_dpm.c4462 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4675 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ci_initialize_mc_reg_table()
H A Dsi_dpm.c5436 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5545 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in si_initialize_mc_reg_table()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c5891 *out_reg = MC_SEQ_MISC_TIMING_LP; in si_check_s0_mc_reg_index()
6000 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in si_initialize_mc_reg_table()