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Searched refs:NO_REGS (Results 1 – 25 of 58) sorted by relevance

123

/dragonfly/contrib/gcc-8.0/gcc/config/i386/
H A Dconstraints.md88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
91 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
97 (define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS"
138 : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
139 : NO_REGS"
146 : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
147 : NO_REGS"
159 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
164 ? NO_REGS : GENERAL_REGS"
175 "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
[all …]
/dragonfly/contrib/gcc-4.7/gcc/config/i386/
H A Dconstraints.md70 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
74 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
82 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
85 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
97 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
101 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
105 "TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS"
109 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
115 ? GENERAL_REGS : NO_REGS"
119 "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS"
[all …]
/dragonfly/contrib/gcc-8.0/gcc/
H A Dira-costs.c544 classes[i] = NO_REGS; in record_reg_classes()
770 if (cl != NO_REGS) in record_reg_classes()
931 if (op_class == NO_REGS) in record_reg_classes()
954 if (op_class != NO_REGS) in record_reg_classes()
972 == NO_REGS) in record_reg_classes()
1829 alt_class = NO_REGS; in find_costs_and_classes()
1907 alt_class = NO_REGS; in find_costs_and_classes()
1921 ? NO_REGS : best); in find_costs_and_classes()
1934 best = NO_REGS; in find_costs_and_classes()
2115 ira_assert (pref[i] == NO_REGS || aclass != NO_REGS); in setup_allocno_class_and_costs()
[all …]
H A Dlra-constraints.c181 if (rclass == NO_REGS) in get_try_hard_regno()
231 return NO_REGS; in get_reg_class()
251 *new_class = NO_REGS; in in_class_p()
1110 if (cl == NO_REGS) in reg_class_from_constraints()
1205 if (sclass == NO_REGS && dclass == NO_REGS) in check_and_process_move()
1208 && ((sclass != NO_REGS && dclass != NO_REGS) in check_and_process_move()
1238 if (sclass != NO_REGS) in check_and_process_move()
1243 if (sclass == NO_REGS in check_and_process_move()
1673 rclass = NO_REGS; in simplify_operand_subreg()
1836 if (cl == NO_REGS) in reg_in_class_p()
[all …]
H A Dira-lives.c698 def_cl = NO_REGS; in make_early_clobber_and_input_conflicts()
761 cl = NO_REGS; in single_reg_class()
772 return NO_REGS; in single_reg_class()
780 return NO_REGS; in single_reg_class()
785 return NO_REGS; in single_reg_class()
789 if (cl == NO_REGS in single_reg_class()
793 return NO_REGS; in single_reg_class()
802 if (cl == NO_REGS in single_reg_class()
806 return NO_REGS; in single_reg_class()
820 return NO_REGS; in single_reg_operand_class()
[all …]
H A Dira.c541 if (i == (int) NO_REGS) in setup_reg_subclasses()
579 if (cl != (int) NO_REGS) in setup_class_subset_and_memory_move_costs()
746 ira_stack_reg_pressure_class = NO_REGS; in setup_stack_reg_pressure_class()
909 if (REGNO_REG_CLASS (i) == NO_REGS) in setup_pressure_classes()
1097 class_translate[cl] = NO_REGS; in setup_class_translate_array()
1105 if (class_translate[cl] == NO_REGS) in setup_class_translate_array()
1114 if (cl == NO_REGS || class_translate[cl] != NO_REGS) in setup_class_translate_array()
1116 best_class = NO_REGS; in setup_class_translate_array()
1172 if (tcl1 != NO_REGS && tcl2 != NO_REGS in comp_reg_classes_func()
1448 ? NO_REGS in setup_hard_regno_aclass()
[all …]
H A Dregrename.c393 has_preferred_class = (preferred_class != NO_REGS); in find_rename_reg()
438 reg_class super_class = NO_REGS; in regrename_find_superclass()
609 chain = create_new_chain (i, iri->nregs, NULL, NULL, NO_REGS); in init_rename_info()
1141 if (cl == NO_REGS || (!exact_match && !DEBUG_INSN_P (insn))) in scan_rtx_reg()
1734 NO_REGS); in build_def_use()
1758 scan_rtx (insn, &PATTERN (insn), NO_REGS, mark_all_read, OP_IN); in build_def_use()
1764 NO_REGS, mark_all_read, OP_IN); in build_def_use()
1778 scan_rtx (insn, loc, NO_REGS, mark_all_read, OP_IN); in build_def_use()
1830 scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, in build_def_use()
1881 scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, in build_def_use()
[all …]
H A Dreload.c366 if (rclass != NO_REGS) in push_secondary_reload()
967 subreg_in_class = NO_REGS; in push_reload()
1088 == NO_REGS)) in push_reload()
1180 == NO_REGS)) in push_reload()
2947 : NO_REGS); in find_reloads()
3414 if (cl != NO_REGS) in find_reloads()
3548 == NO_REGS) in find_reloads()
3576 == NO_REGS) in find_reloads()
3582 == NO_REGS)) in find_reloads()
3925 == NO_REGS) in find_reloads()
[all …]
H A Dtarghooks.c1059 return NO_REGS; in default_branch_target_register_class()
1100 enum reg_class rclass = NO_REGS; in default_secondary_reload()
1106 return NO_REGS; in default_secondary_reload()
1118 if (rclass != NO_REGS) in default_secondary_reload()
1145 gcc_assert (insn_class != NO_REGS); in default_secondary_reload()
1164 rclass = NO_REGS; in default_secondary_reload()
1170 if (rclass == NO_REGS) in default_secondary_reload()
1848 return NO_REGS; in default_preferred_rename_class()
H A Dlra-assigns.c618 lra_assert (rclass != NO_REGS); in find_hard_regno_for_1()
904 && reg_alternate_class (spill_regno) == NO_REGS) in must_not_spill_p()
942 lra_assert (reg_renumber[regno] < 0 && rclass != NO_REGS); in spill_for()
1373 && regno_allocno_class_array[i] != NO_REGS) in assign_by_spills()
1520 && regno_allocno_class_array[i] != NO_REGS) in assign_by_spills()
1550 PSEUDO_REGNO_MODE (regno)))) == NO_REGS) in assign_by_spills()
1760 && (rclass = lra_get_allocno_class (i)) != NO_REGS in lra_split_hard_reg_for()
H A Dreginfo.c344 if (i == (int) NO_REGS) in init_reg_sets_1()
390 if (REGNO_REG_CLASS (i) == NO_REGS) in init_reg_sets_1()
599 if (altclass == NO_REGS) in memory_move_secondary_cost()
883 return NO_REGS; in reg_allocno_class()
H A Dira-color.c1271 && ALLOCNO_CLASS (allocno) != NO_REGS) in queue_update_cost()
2233 && ALLOCNO_CLASS (a) != NO_REGS) in add_allocno_to_bucket()
2359 && ALLOCNO_CLASS (allocno) != NO_REGS) in delete_allocno_from_bucket()
2393 if (aclass == NO_REGS) in push_allocno_to_stack()
2604 if (ALLOCNO_CLASS (a) != NO_REGS) in push_allocnos_to_stack()
2643 if (aclass == NO_REGS) in pop_allocnos_from_stack()
2681 if (aclass == NO_REGS) in setup_allocno_available_regs_num()
3116 if (ALLOCNO_CLASS (a) == NO_REGS) in color_allocnos()
3606 if (aclass == NO_REGS) in update_curr_costs()
3670 if (ALLOCNO_CLASS (a) != NO_REGS) in ira_reassign_conflict_allocnos()
[all …]
H A Dloop-invariant.c665 || REGNO_REG_CLASS (REGNO (x)) != NO_REGS)); in may_assign_reg_p()
1277 pressure_class = NO_REGS; in get_pressure_class_and_nregs()
1460 enum reg_class cl = NO_REGS; in gain_for_invariant()
1476 else if ((ret == 0) && (cl == NO_REGS)) in gain_for_invariant()
1888 GENERAL_REGS, NO_REGS, GENERAL_REGS); in move_invariants()
2005 return NO_REGS; in get_regno_pressure_class()
H A Dlra-spills.c268 PSEUDO_REGNO_MODE (regno)))) == NO_REGS in assign_spill_hard_regs()
275 lra_assert (spill_class != NO_REGS); in assign_spill_hard_regs()
H A Dstmt.c298 if (reg_class_for_constraint (cn) != NO_REGS in parse_output_constraint()
420 if (reg_class_for_constraint (cn) != NO_REGS in parse_input_constraint()
H A Dlra-int.h445 setup_reg_classes (regno, new_class, NO_REGS, new_class); in lra_change_class()
/dragonfly/contrib/gcc-4.7/gcc/
H A Dira-lives.c670 def_cl = NO_REGS; in make_early_clobber_and_input_conflicts()
733 cl = NO_REGS; in single_reg_class()
760 return NO_REGS; in single_reg_class()
770 return NO_REGS; in single_reg_class()
781 return NO_REGS; in single_reg_class()
798 return NO_REGS; in single_reg_class()
811 return NO_REGS; in single_reg_class()
822 return NO_REGS; in single_reg_class()
856 return NO_REGS; in single_reg_class()
868 return NO_REGS; in single_reg_operand_class()
[all …]
H A Dira-costs.c360 if (secondary_class != NO_REGS) in copy_cost()
451 classes[i] = NO_REGS; in record_reg_classes()
507 if (classes[j] == NO_REGS) in record_reg_classes()
859 == NO_REGS) in record_reg_classes()
1681 alt_class = NO_REGS; in find_costs_and_classes()
1730 best = alt_class = NO_REGS; in find_costs_and_classes()
1732 alt_class = NO_REGS; in find_costs_and_classes()
1753 best = NO_REGS; in find_costs_and_classes()
1916 ira_assert (pref[i] == NO_REGS || aclass != NO_REGS); in setup_allocno_class_and_costs()
1919 if (aclass == NO_REGS) in setup_allocno_class_and_costs()
[all …]
H A Dira.c544 if (i == (int) NO_REGS) in setup_reg_subclasses()
578 ira_memory_move_cost[mode][NO_REGS][0] in setup_class_subset_and_memory_move_costs()
582 if (cl != (int) NO_REGS) in setup_class_subset_and_memory_move_costs()
749 ira_stack_reg_pressure_class = NO_REGS; in setup_stack_reg_pressure_class()
905 if (REGNO_REG_CLASS (i) == NO_REGS) in setup_pressure_classes()
1060 class_translate[cl] = NO_REGS; in setup_class_translate_array()
1068 if (class_translate[cl] == NO_REGS) in setup_class_translate_array()
1077 if (cl == NO_REGS || class_translate[cl] != NO_REGS) in setup_class_translate_array()
1079 best_class = NO_REGS; in setup_class_translate_array()
1135 if (tcl1 != NO_REGS && tcl2 != NO_REGS in comp_reg_classes_func()
[all …]
H A Dtarghooks.c834 return NO_REGS; in default_branch_target_register_class()
843 enum reg_class rclass = NO_REGS; in default_secondary_reload()
849 return NO_REGS; in default_secondary_reload()
859 if (rclass != NO_REGS) in default_secondary_reload()
890 gcc_assert (insn_class != NO_REGS); in default_secondary_reload()
912 rclass = NO_REGS; in default_secondary_reload()
918 if (rclass == NO_REGS) in default_secondary_reload()
1296 return NO_REGS; in default_preferred_rename_class()
H A Dregrename.c384 has_preferred_class = (preferred_class != NO_REGS); in find_best_rename_reg()
440 enum reg_class super_class = NO_REGS; in rename_chains()
461 super_class = NO_REGS; in rename_chains()
584 chain = create_new_chain (i, iri->nregs, NULL, NULL_RTX, NO_REGS); in init_rename_info()
1073 if (cl == NO_REGS || (!exact_match && !DEBUG_INSN_P (insn))) in scan_rtx_reg()
1636 NO_REGS); in build_def_use()
1661 scan_rtx (insn, &PATTERN (insn), NO_REGS, mark_all_read, OP_IN); in build_def_use()
1667 NO_REGS, mark_all_read, OP_IN); in build_def_use()
1681 scan_rtx (insn, loc, NO_REGS, mark_all_read, OP_IN); in build_def_use()
1726 scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, in build_def_use()
[all …]
H A Dreload.c375 if (rclass != NO_REGS) in push_secondary_reload()
568 gcc_assert (rclass != NO_REGS); in scratch_reload_class()
1061 == NO_REGS)) in push_reload()
1154 == NO_REGS)) in push_reload()
1307 gcc_assert (rclass != NO_REGS in push_reload()
2917 : NO_REGS); in find_reloads()
3517 == NO_REGS) in find_reloads()
3544 == NO_REGS) in find_reloads()
3550 == NO_REGS)) in find_reloads()
3923 == NO_REGS) in find_reloads()
[all …]
H A Dira-color.c1203 && ALLOCNO_CLASS (allocno) != NO_REGS) in queue_update_cost()
1249 if (aclass == NO_REGS) in update_copy_costs()
1769 && ALLOCNO_CLASS (a) != NO_REGS) in add_allocno_to_bucket()
1855 && ALLOCNO_CLASS (allocno) != NO_REGS) in add_allocno_to_ordered_bucket()
1917 if (aclass == NO_REGS) in push_allocno_to_stack()
2118 if (ALLOCNO_CLASS (a) != NO_REGS) in push_allocnos_to_stack()
2157 if (aclass == NO_REGS) in pop_allocnos_from_stack()
2193 if (aclass == NO_REGS) in setup_allocno_available_regs_num()
2565 if (ALLOCNO_CLASS (a) == NO_REGS) in color_allocnos()
3043 if (aclass == NO_REGS) in update_curr_costs()
[all …]
H A Dreginfo.c435 if (i == (int) NO_REGS) in init_reg_sets_1()
481 if (REGNO_REG_CLASS (i) == NO_REGS) in init_reg_sets_1()
695 if (altclass == NO_REGS) in memory_move_secondary_cost()
981 return NO_REGS; in reg_allocno_class()
H A Dloop-invariant.c653 || REGNO_REG_CLASS (REGNO (x)) != NO_REGS)); in may_assign_reg_p()
1032 pressure_class = NO_REGS; in get_pressure_class_and_nregs()
1529 GENERAL_REGS, NO_REGS, GENERAL_REGS); in move_invariants()
1646 return NO_REGS; in get_regno_pressure_class()

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