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Searched refs:PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h677 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e macro
H A Dbif_4_1_sh_mask.h3622 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e macro
H A Dbif_5_0_sh_mask.h4072 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e macro