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Searched refs:PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h4811 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d macro
H A Dbif_4_1_sh_mask.h6388 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d macro
H A Dbif_5_0_sh_mask.h6926 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d macro