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Searched refs:PPSMC_MSG_SCLKDPM_SetEnabledMask (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dppsmc.h130 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) macro
H A Dkv_dpm.c2409 PPSMC_MSG_SCLKDPM_SetEnabledMask, in kv_set_enabled_level()
2422 PPSMC_MSG_SCLKDPM_SetEnabledMask, in kv_set_enabled_levels()
H A Dci_dpm.c1738 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); in ci_dpm_force_state_sclk()
3859 PPSMC_MSG_SCLKDPM_SetEnabledMask, in ci_upload_dpm_level_enable_mask()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dppsmc.h133 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) macro
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dfiji_ppsmc.h245 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) macro
H A Dsmu7_ppsmc.h242 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) macro
H A Dtonga_ppsmc.h269 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) macro
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c2630 PPSMC_MSG_SCLKDPM_SetEnabledMask, in smu7_force_dpm_highest()
2663 PPSMC_MSG_SCLKDPM_SetEnabledMask, in smu7_upload_dpm_level_enable_mask()
2703 PPSMC_MSG_SCLKDPM_SetEnabledMask, in smu7_force_dpm_lowest()
4397 PPSMC_MSG_SCLKDPM_SetEnabledMask, in smu7_force_clock_level()