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Searched refs:RB_NO_UPDATE (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v5_0_start()
H A Duvd_v6_0.c831 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v6_0_start()
H A Dvcn_v1_0.c738 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in vcn_v1_0_start()
H A Duvd_v7_0.c1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v7_0_start()
/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h352 #define RB_NO_UPDATE (1 << 27) macro
H A Dnid.h487 #define RB_NO_UPDATE (1 << 27) macro
H A Dsid.h1250 #define RB_NO_UPDATE (1 << 27) macro
H A Dcikd.h1306 #define RB_NO_UPDATE (1 << 27) macro
H A Drv770.c1098 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
H A Devergreend.h479 #define RB_NO_UPDATE (1 << 27) macro
H A Dr600d.h198 #define RB_NO_UPDATE (1 << 27) macro
H A Dr600.c2667 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
2765 tmp |= RB_NO_UPDATE; in r600_cp_resume()
H A Devergreen.c2960 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()
3092 tmp |= RB_NO_UPDATE; in evergreen_cp_resume()
H A Dsi.c3674 tmp |= RB_NO_UPDATE; in si_cp_resume()
H A Dcik.c4129 tmp |= RB_NO_UPDATE; in cik_cp_gfx_resume()