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Searched refs:REG_WRITE (Results 1 – 21 of 21) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_abm.c244 REG_WRITE(BIOS_SCRATCH_2, s2); in dmcu_set_backlight_level()
256 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); in dce_abm_init()
257 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); in dce_abm_init()
258 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); in dce_abm_init()
259 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); in dce_abm_init()
356 REG_WRITE(BL_PWM_CNTL, in dce_abm_init_backlight()
358 REG_WRITE(BL_PWM_CNTL2, in dce_abm_init_backlight()
360 REG_WRITE(BL_PWM_PERIOD_CNTL, in dce_abm_init_backlight()
370 REG_WRITE(BL_PWM_CNTL, 0xC000FA00); in dce_abm_init_backlight()
371 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); in dce_abm_init_backlight()
[all …]
H A Ddce_dmcu.c79 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); in dce_dmcu_load_iram()
82 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); in dce_dmcu_load_iram()
104 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); in dce_get_dmcu_psr_state()
334 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset); in dcn10_get_dmcu_state()
351 REG_WRITE(DC_DMCU_SCRATCH, 0); in dcn10_get_dmcu_version()
361 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); in dcn10_get_dmcu_version()
420 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); in dcn10_dmcu_init()
461 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); in dcn10_dmcu_load_iram()
464 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); in dcn10_dmcu_load_iram()
503 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); in dcn10_get_dmcu_psr_state()
H A Ddce_stream_encoder.c122 REG_WRITE(AFMT_GENERIC_0, *content++); in dce110_update_generic_info_packet()
123 REG_WRITE(AFMT_GENERIC_1, *content++); in dce110_update_generic_info_packet()
124 REG_WRITE(AFMT_GENERIC_2, *content++); in dce110_update_generic_info_packet()
125 REG_WRITE(AFMT_GENERIC_3, *content++); in dce110_update_generic_info_packet()
126 REG_WRITE(AFMT_GENERIC_4, *content++); in dce110_update_generic_info_packet()
127 REG_WRITE(AFMT_GENERIC_5, *content++); in dce110_update_generic_info_packet()
128 REG_WRITE(AFMT_GENERIC_6, *content++); in dce110_update_generic_info_packet()
129 REG_WRITE(AFMT_GENERIC_7, *content); in dce110_update_generic_info_packet()
721 REG_WRITE(AFMT_AVI_INFO0, content[0]); in dce110_stream_encoder_update_hdmi_info_packets()
723 REG_WRITE(AFMT_AVI_INFO1, content[1]); in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
H A Ddce_transform.c232 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl); in program_multi_taps_filter()
301 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); in program_scl_ratios_inits()
336 REG_WRITE(SCL_F_SHARP_CONTROL, 0); in dce_transform_set_scaler()
1184 REG_WRITE(REGAMMA_LUT_INDEX, 0); in program_pwl()
1189 REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); in program_pwl()
1190 REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); in program_pwl()
1191 REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); in program_pwl()
1192 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); in program_pwl()
1193 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); in program_pwl()
1194 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); in program_pwl()
H A Ddce_opp.c294 REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0); in set_temporal_dither()
296 REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0); in set_temporal_dither()
298 REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0); in set_temporal_dither()
H A Ddce_hwseq.c83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
H A Ddce_aux.c115 REG_WRITE(AUX_CONTROL, value); in acquire_engine()
129 REG_WRITE(AUX_CONTROL, value); in acquire_engine()
H A Ddce_link_encoder.c240 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); in dce110_link_encoder_set_dp_phy_pattern_training_pattern()
280 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); in setup_panel_mode()
H A Ddce_clock_source.c919 REG_WRITE(PHASE[inst], clock_kHz); in dce110_program_pix_clk()
920 REG_WRITE(MODULO[inst], dp_dto_ref_kHz); in dce110_program_pix_clk()
H A Ddce_audio.c569 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, in dce_aud_az_configure()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hubbub.c219 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); in hubbub1_program_watermarks()
230 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); in hubbub1_program_watermarks()
244 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); in hubbub1_program_watermarks()
257 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); in hubbub1_program_watermarks()
282 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); in hubbub1_program_watermarks()
307 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); in hubbub1_program_watermarks()
320 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); in hubbub1_program_watermarks()
345 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); in hubbub1_program_watermarks()
383 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); in hubbub1_program_watermarks()
408 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); in hubbub1_program_watermarks()
[all …]
H A Ddcn10_stream_encoder.c110 REG_WRITE(AFMT_GENERIC_0, *content++); in enc1_update_generic_info_packet()
111 REG_WRITE(AFMT_GENERIC_1, *content++); in enc1_update_generic_info_packet()
112 REG_WRITE(AFMT_GENERIC_2, *content++); in enc1_update_generic_info_packet()
113 REG_WRITE(AFMT_GENERIC_3, *content++); in enc1_update_generic_info_packet()
114 REG_WRITE(AFMT_GENERIC_4, *content++); in enc1_update_generic_info_packet()
115 REG_WRITE(AFMT_GENERIC_5, *content++); in enc1_update_generic_info_packet()
116 REG_WRITE(AFMT_GENERIC_6, *content++); in enc1_update_generic_info_packet()
117 REG_WRITE(AFMT_GENERIC_7, *content); in enc1_update_generic_info_packet()
411 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ in enc1_stream_encoder_dp_set_stream_attribute()
H A Ddcn10_optc.c685 REG_WRITE(OTG_TRIGA_CNTL, 0); in optc1_disable_reset_trigger()
982 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); in optc1_set_test_pattern()
1106 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); in optc1_set_test_pattern()
1109 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); in optc1_set_test_pattern()
1120 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); in optc1_set_test_pattern()
1121 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); in optc1_set_test_pattern()
1122 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); in optc1_set_test_pattern()
1336 REG_WRITE(OTG_CRC_CNTL, 0); in optc1_configure_crc()
H A Ddcn10_hw_sequencer.c396 REG_WRITE(D1VGA_CONTROL, 0); in disable_vga()
397 REG_WRITE(D2VGA_CONTROL, 0); in disable_vga()
398 REG_WRITE(D3VGA_CONTROL, 0); in disable_vga()
399 REG_WRITE(D4VGA_CONTROL, 0); in disable_vga()
965 REG_WRITE(REFCLK_CNTL, 0); in dcn10_init_hw()
967 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn10_init_hw()
971 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); in dcn10_init_hw()
973 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dcn10_init_hw()
1084 REG_WRITE(DIO_MEM_PWR_CTRL, 0); in dcn10_init_hw()
1088 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); in dcn10_init_hw()
[all …]
H A Ddcn10_link_encoder.c211 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); in dcn10_link_encoder_set_dp_phy_pattern_training_pattern()
246 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); in setup_panel_mode()
H A Ddcn10_hubp.c130 REG_WRITE(HUBPREQ_DEBUG_DB, value); in hubp1_vready_workaround()
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c1717 REG_WRITE(AR_SOC_RST_RESET, in ar9300_set_reset()
1719 REG_WRITE(AR_SOC_RST_RESET, in ar9300_set_reset()
1738 #undef REG_WRITE in ar9300_set_reset()
1828 #undef REG_WRITE in ar9300_set_reset()
1978 #undef REG_WRITE in ar9300_phy_disable()
3069 REG_WRITE(0xB8040000, val); in ar9300_process_ini()
3074 REG_WRITE(0xB804002c, val); in ar9300_process_ini()
3078 REG_WRITE(0xB804006c, val); in ar9300_process_ini()
3080 #undef REG_WRITE in ar9300_process_ini()
5247 #undef REG_WRITE in ar9300_reset()
[all …]
H A Dar9300_attach.c772 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); in ar9300_attach() macro
784 #undef REG_WRITE in ar9300_attach()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5312/
H A Dar5312reg.h31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); macro
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce110/
H A Daux_engine_dce110.c145 REG_WRITE(AUX_CONTROL, value); in acquire_engine()
159 REG_WRITE(AUX_CONTROL, value); in acquire_engine()
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Dreg_helper.h42 #define REG_WRITE(reg_name, value) \ macro