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Searched refs:RE_CFG2 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/netif/re/
H A Dre.h116 #define RE_CFG2 0x0053 /* config register #2 */ macro
H A Dre.c1151 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7); in DisableMcuBPs()
3881 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7); in re_hw_init()
3883 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5); in re_hw_init()
5689 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7); in re_hw_start_unlock()
5754 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | 0x80); in re_hw_start_unlock()
6296 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5); in re_hw_start_unlock()
6561 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5); in re_hw_start_unlock()
7108 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_7); in re_hw_start_unlock()
7251 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7); in re_hw_start_unlock_8125()
7264 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) | BIT_5); in re_hw_start_unlock_8125()
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H A Dif_re.c791 cfg2 = CSR_READ_1(sc, RE_CFG2); in re_attach()