Home
last modified time | relevance | path

Searched refs:SH_MEM_CONFIG (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dcik_sdma.c969 radeon_ring_write(ring, SH_MEM_CONFIG >> 2); in cik_dma_vm_flush()
H A Dcikd.h1171 #define SH_MEM_CONFIG 0x8C34 macro
H A Dcik.c5542 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); in cik_pcie_gart_enable()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c3887 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); in gfx_v8_0_gpu_init()
3888 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); in gfx_v8_0_gpu_init()
3889 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v8_0_gpu_init()
3894 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); in gfx_v8_0_gpu_init()
3895 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); in gfx_v8_0_gpu_init()
3896 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v8_0_gpu_init()
H A Dgfx_v9_0.c1785 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v9_0_gpu_init()
1790 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v9_0_gpu_init()