Searched refs:SKL_DPLL0 (Results 1 – 3 of 3) sorted by relevance
768 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_update()769 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_update()770 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != in skl_dpll0_update()771 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) in skl_dpll0_update()774 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()786 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_update()878 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_enable()879 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_enable()880 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); in skl_dpll0_enable()883 SKL_DPLL0); in skl_dpll0_enable()[all …]
257 #define SKL_DPLL0 0 macro
8931 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) in cannonlake_get_ddi_pll()8971 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) in skylake_get_ddi_pll()