1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HW_SHARED_H__ 27 #define __DAL_HW_SHARED_H__ 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "dc_hw_types.h" 32 33 /****************************************************************************** 34 * Data types shared between different Virtual HW blocks 35 ******************************************************************************/ 36 37 #define MAX_AUDIOS 7 38 #define MAX_PIPES 6 39 40 struct gamma_curve { 41 uint32_t offset; 42 uint32_t segments_num; 43 }; 44 45 struct curve_points { 46 struct fixed31_32 x; 47 struct fixed31_32 y; 48 struct fixed31_32 offset; 49 struct fixed31_32 slope; 50 51 uint32_t custom_float_x; 52 uint32_t custom_float_y; 53 uint32_t custom_float_offset; 54 uint32_t custom_float_slope; 55 }; 56 57 struct pwl_result_data { 58 struct fixed31_32 red; 59 struct fixed31_32 green; 60 struct fixed31_32 blue; 61 62 struct fixed31_32 delta_red; 63 struct fixed31_32 delta_green; 64 struct fixed31_32 delta_blue; 65 66 uint32_t red_reg; 67 uint32_t green_reg; 68 uint32_t blue_reg; 69 70 uint32_t delta_red_reg; 71 uint32_t delta_green_reg; 72 uint32_t delta_blue_reg; 73 }; 74 75 struct pwl_params { 76 struct gamma_curve arr_curve_points[34]; 77 struct curve_points arr_points[2]; 78 struct pwl_result_data rgb_resulted[256 + 3]; 79 uint32_t hw_points_num; 80 }; 81 82 /* move to dpp 83 * while we are moving functionality out of opp to dpp to align 84 * HW programming to HW IP, we define these struct in hw_shared 85 * so we can still compile while refactoring 86 */ 87 88 enum lb_pixel_depth { 89 /* do not change the values because it is used as bit vector */ 90 LB_PIXEL_DEPTH_18BPP = 1, 91 LB_PIXEL_DEPTH_24BPP = 2, 92 LB_PIXEL_DEPTH_30BPP = 4, 93 LB_PIXEL_DEPTH_36BPP = 8 94 }; 95 96 enum graphics_csc_adjust_type { 97 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 98 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 99 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 100 }; 101 102 enum ipp_degamma_mode { 103 IPP_DEGAMMA_MODE_BYPASS, 104 IPP_DEGAMMA_MODE_HW_sRGB, 105 IPP_DEGAMMA_MODE_HW_xvYCC, 106 IPP_DEGAMMA_MODE_USER_PWL 107 }; 108 109 enum ipp_output_format { 110 IPP_OUTPUT_FORMAT_12_BIT_FIX, 111 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 112 IPP_OUTPUT_FORMAT_FLOAT 113 }; 114 115 enum expansion_mode { 116 EXPANSION_MODE_DYNAMIC, 117 EXPANSION_MODE_ZERO 118 }; 119 120 struct default_adjustment { 121 enum lb_pixel_depth lb_color_depth; 122 enum dc_color_space out_color_space; 123 enum dc_color_space in_color_space; 124 enum dc_color_depth color_depth; 125 enum pixel_format surface_pixel_format; 126 enum graphics_csc_adjust_type csc_adjust_type; 127 bool force_hw_default; 128 }; 129 130 131 struct out_csc_color_matrix { 132 enum dc_color_space color_space; 133 uint16_t regval[12]; 134 }; 135 136 137 enum opp_regamma { 138 OPP_REGAMMA_BYPASS = 0, 139 OPP_REGAMMA_SRGB, 140 OPP_REGAMMA_XVYCC, 141 OPP_REGAMMA_USER 142 }; 143 144 struct dc_bias_and_scale { 145 uint16_t scale_red; 146 uint16_t bias_red; 147 uint16_t scale_green; 148 uint16_t bias_green; 149 uint16_t scale_blue; 150 uint16_t bias_blue; 151 }; 152 153 enum test_pattern_dyn_range { 154 TEST_PATTERN_DYN_RANGE_VESA = 0, 155 TEST_PATTERN_DYN_RANGE_CEA 156 }; 157 158 enum test_pattern_mode { 159 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 160 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 161 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 162 TEST_PATTERN_MODE_VERTICALBARS, 163 TEST_PATTERN_MODE_HORIZONTALBARS, 164 TEST_PATTERN_MODE_SINGLERAMP_RGB, 165 TEST_PATTERN_MODE_DUALRAMP_RGB 166 }; 167 168 enum test_pattern_color_format { 169 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 170 TEST_PATTERN_COLOR_FORMAT_BPC_8, 171 TEST_PATTERN_COLOR_FORMAT_BPC_10, 172 TEST_PATTERN_COLOR_FORMAT_BPC_12 173 }; 174 175 enum controller_dp_test_pattern { 176 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 177 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 178 CONTROLLER_DP_TEST_PATTERN_PRBS7, 179 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 180 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 181 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 182 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 183 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 184 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 185 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 186 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 187 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA 188 }; 189 190 enum dc_lut_mode { 191 LUT_BYPASS, 192 LUT_RAM_A, 193 LUT_RAM_B 194 }; 195 #endif /* __DAL_HW_SHARED_H__ */ 196