Searched refs:clear_state_gpu_addr (Results 1 – 7 of 7) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfx_v9_0.c | 925 (u64 *)&adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_rlc_fini() 951 (u64 *)&adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_rlc_init() 1003 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v9_0_csb_vram_pin() 1653 (u64 *)&adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini() 1862 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb() 1864 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
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H A D | amdgpu.h | 717 uint64_t clear_state_gpu_addr; member
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H A D | gfx_v8_0.c | 1393 (u64 *)&adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_rlc_init() 2213 (u64 *)&adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini() 3994 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb() 3996 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | evergreen.c | 4248 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init() 4267 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init() 4274 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init() 4394 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
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H A D | si.c | 5275 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg() 5772 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg() 5778 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
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H A D | radeon.h | 1008 u64 clear_state_gpu_addr; member
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H A D | cik.c | 6666 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg() 6667 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
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