1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: src/sys/dev/ic/ns16550.h,v 1.14 2003/09/16 14:21:17 bde Exp $ 31 * $DragonFly: src/sys/dev/serial/ic_layer/ns16550.h,v 1.4 2005/09/01 00:18:24 swildner Exp $ 32 */ 33 34 /* 35 * NS8250... UART registers. 36 */ 37 38 /* 8250 registers #[0-6]. */ 39 40 #define com_data 0 /* data register (R/W) */ 41 #define com_thr com_data /* transmitter holding register (W) */ 42 #define com_rhr com_data /* receiver holding register (R) */ 43 44 #define com_ier 1 /* interrupt enable register (W) */ 45 #define IER_ERXRDY 0x1 46 #define IER_ETXRDY 0x2 47 #define IER_ERLS 0x4 48 #define IER_EMSC 0x8 49 50 #define com_iir 2 /* interrupt identification register (R) */ 51 #define com_isr com_iir /* interrupt status register (R) */ 52 #define IIR_IMASK 0xf 53 #define IIR_RXTOUT 0xc 54 #define IIR_RLS 0x6 55 #define IIR_RXRDY 0x4 56 #define IIR_TXRDY 0x2 57 #define IIR_NOPEND 0x1 58 #define IIR_MLSC 0x0 59 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 60 61 #define com_lcr 3 /* line control register (R/W) */ 62 #define com_lctl com_lcr 63 #define com_cfcr com_lcr /* character format control register (R/W) */ 64 #define LCR_DLAB 0x80 65 #define CFCR_DLAB LCR_DLAB 66 #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 67 #define CFCR_EFR_ENABLE LCR_EFR_ENABLE 68 #define CFCR_SBREAK 0x40 69 #define CFCR_PZERO 0x30 70 #define CFCR_PONE 0x20 71 #define CFCR_PEVEN 0x10 72 #define CFCR_PODD 0x00 73 #define CFCR_PENAB 0x08 74 #define CFCR_STOPB 0x04 75 #define CFCR_8BITS 0x03 76 #define CFCR_7BITS 0x02 77 #define CFCR_6BITS 0x01 78 #define CFCR_5BITS 0x00 79 80 #define com_mcr 4 /* modem control register (R/W) */ 81 #define MCR_PRESCALE 0x80 /* only available on 16650 up */ 82 #define MCR_LOOPBACK 0x10 83 #define MCR_IENABLE 0x08 84 #define MCR_DRS 0x04 85 #define MCR_RTS 0x02 86 #define MCR_DTR 0x01 87 88 #define com_lsr 5 /* line status register (R/W) */ 89 #define LSR_RCV_FIFO 0x80 90 #define LSR_TSRE 0x40 91 #define LSR_TXRDY 0x20 92 #define LSR_BI 0x10 93 #define LSR_FE 0x08 94 #define LSR_PE 0x04 95 #define LSR_OE 0x02 96 #define LSR_RXRDY 0x01 97 #define LSR_RCV_MASK 0x1f 98 99 #define com_msr 6 /* modem status register (R/W) */ 100 #define MSR_DCD 0x80 101 #define MSR_RI 0x40 102 #define MSR_DSR 0x20 103 #define MSR_CTS 0x10 104 #define MSR_DDCD 0x08 105 #define MSR_TERI 0x04 106 #define MSR_DDSR 0x02 107 #define MSR_DCTS 0x01 108 109 /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 110 #define com_dll 0 /* divisor latch low (R/W) */ 111 #define com_dlbl com_dll 112 #define com_dlm 1 /* divisor latch high (R/W) */ 113 #define com_dlbh com_dlm 114 115 /* 16450 register #7. Not multiplexed. */ 116 #define com_scr 7 /* scratch register (R/W) */ 117 118 /* 16550 register #2. Not multiplexed. */ 119 #define com_fcr 2 /* FIFO control register (W) */ 120 #define com_fifo com_fcr 121 #define FIFO_ENABLE 0x01 122 #define FIFO_RCV_RST 0x02 123 #define FIFO_XMT_RST 0x04 124 #define FIFO_DMA_MODE 0x08 125 #define FIFO_RX_LOW 0x00 126 #define FIFO_RX_MEDL 0x40 127 #define FIFO_RX_MEDH 0x80 128 #define FIFO_RX_HIGH 0xc0 129 130 /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 131 132 #define com_efr 2 /* enhanced features register (R/W) */ 133 #define EFR_AUTOCTS 0x80 134 #define EFR_AUTORTS 0x40 135 #define EFR_EFE 0x10 /* enhanced functions enable */ 136 137 #define com_xon1 4 /* XON 1 character (R/W) */ 138 #define com_xon2 5 /* XON 2 character (R/W) */ 139 #define com_xoff1 6 /* XOFF 1 character (R/W) */ 140 #define com_xoff2 7 /* XOFF 2 character (R/W) */ 141 142 /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 143 #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 144 145 /* 16950 register #3. R/W access enabled by ACR[7]. */ 146 #define com_rfl 3 /* receiver fifo level (R) */ 147 148 /* 149 * 16950 register #4. Access enabled by ACR[7]. Also requires 150 * !LCR_EFR_ENABLE. 151 */ 152 #define com_tfl 4 /* transmitter fifo level (R) */ 153 154 /* 155 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 156 * requires ACR[6]. 157 */ 158 #define com_icr 5 /* index control register (R/W) */ 159 160 /* 161 * 16950 register #7. It is the same as com_scr except it has a different 162 * abbreviation in the manufacturer's data sheet and it also serves as an 163 * index into the Indexed Control register set. 164 */ 165 #define com_spr com_scr /* scratch pad (and index) register (R/W) */ 166 167 /* 168 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 169 * data in ICR (if ICR is accessible). 170 */ 171 172 #define com_acr 0 /* additional control register (R/W) */ 173 #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 174 #define ACR_ICRE 0x40 /* ICR enable */ 175 #define ACR_TLE 0x20 /* TTL/RTL enable */ 176 177 #define com_cpr 1 /* clock prescaler register (R/W) */ 178 #define com_tcr 2 /* times clock register (R/W) */ 179 #define com_ttl 4 /* transmitter trigger level (R/W) */ 180 #define com_rtl 5 /* receiver trigger level (R/W) */ 181 /* ... */ 182