/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | atombios_crtc.c | 58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup() 59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup() 62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup() 63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup() 66 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in amdgpu_atombios_crtc_overscan_setup() 67 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in amdgpu_atombios_crtc_overscan_setup() 69 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in amdgpu_atombios_crtc_overscan_setup() 70 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in amdgpu_atombios_crtc_overscan_setup() 201 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing() 203 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing() [all …]
|
H A D | amdgpu_encoders.c | 175 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup() 178 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; in amdgpu_panel_mode_fixup() 179 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; in amdgpu_panel_mode_fixup()
|
H A D | dce_v10_0.c | 595 if (mode->crtc_hdisplay < 1920) { in dce_v10_0_line_buffer_adjust() 598 } else if (mode->crtc_hdisplay < 2560) { in dce_v10_0_line_buffer_adjust() 601 } else if (mode->crtc_hdisplay < 4096) { in dce_v10_0_line_buffer_adjust() 1024 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v10_0_program_watermarks() 1042 wm_high.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks() 1081 wm_low.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks() 1107 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v10_0_program_watermarks()
|
H A D | dce_v11_0.c | 621 if (mode->crtc_hdisplay < 1920) { in dce_v11_0_line_buffer_adjust() 624 } else if (mode->crtc_hdisplay < 2560) { in dce_v11_0_line_buffer_adjust() 627 } else if (mode->crtc_hdisplay < 4096) { in dce_v11_0_line_buffer_adjust() 1050 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v11_0_program_watermarks() 1068 wm_high.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks() 1107 wm_low.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks() 1133 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v11_0_program_watermarks()
|
/dragonfly/sys/dev/drm/i915/ |
H A D | intel_panel.c | 121 x = (adjusted_mode->crtc_hdisplay - width + 1)/2; in intel_pch_panel_fitting() 128 u32 scaled_width = adjusted_mode->crtc_hdisplay in intel_pch_panel_fitting() 136 x = (adjusted_mode->crtc_hdisplay - width + 1) / 2; in intel_pch_panel_fitting() 145 width = adjusted_mode->crtc_hdisplay; in intel_pch_panel_fitting() 148 width = adjusted_mode->crtc_hdisplay; in intel_pch_panel_fitting() 156 width = adjusted_mode->crtc_hdisplay; in intel_pch_panel_fitting() 182 border = (adjusted_mode->crtc_hdisplay - width + 1) / 2; in centre_horizontally() 185 adjusted_mode->crtc_hdisplay = width; in centre_horizontally() 231 u32 scaled_width = adjusted_mode->crtc_hdisplay * in i965_scale_aspect() 252 u32 scaled_width = adjusted_mode->crtc_hdisplay * in i9xx_scale_aspect() [all …]
|
H A D | intel_dsi.c | 1119 adjusted_mode->crtc_hdisplay = in bxt_dsi_get_pipe_config() 1126 hactive = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config() 1156 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config() 1158 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config() 1179 adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config() 1212 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + in bxt_dsi_get_pipe_config() 1214 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config() 1216 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config() 1311 hactive = adjusted_mode->crtc_hdisplay; in set_dsi_timings() 1346 adjusted_mode->crtc_hdisplay); in set_dsi_timings() [all …]
|
H A D | dvo_ivch.c | 417 if (mode->hdisplay != adjusted_mode->crtc_hdisplay || in ivch_mode_set() 424 (adjusted_mode->crtc_hdisplay - 1)) >> 2; in ivch_mode_set()
|
H A D | intel_fbdev.c | 612 cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay; in intel_fbdev_init_bios() 627 intel_crtc->config->base.adjusted_mode.crtc_hdisplay, in intel_fbdev_init_bios()
|
H A D | intel_dvo.c | 291 (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | in intel_dvo_pre_enable()
|
H A D | dvo_ns2501.c | 576 adjusted_mode->crtc_hdisplay, in ns2501_mode_set()
|
H A D | intel_psr.c | 428 if (adjusted_mode->crtc_hdisplay > 3200 || in intel_psr_compute_config()
|
H A D | intel_display.c | 4701 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); in skl_update_scaler_crtc() 6327 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) in intel_crtc_compute_config() 6971 (adjusted_mode->crtc_hdisplay - 1) | in intel_set_pipe_timings() 7023 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings() 7067 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config() 10575 mode->crtc_hdisplay, mode->crtc_hsync_start, in intel_dump_crtc_timings() 11218 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); in intel_pipe_config_compare()
|
H A D | intel_hdmi.c | 637 return mode->crtc_hdisplay % pixels_per_group == 0 && in gcp_default_phase_possible()
|
/dragonfly/sys/dev/drm/radeon/ |
H A D | atombios_crtc.c | 54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup() 55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup() 58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in atombios_overscan_setup() 59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in atombios_overscan_setup() 62 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in atombios_overscan_setup() 63 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in atombios_overscan_setup() 65 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in atombios_overscan_setup() 311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing() 313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing() 318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing() [all …]
|
H A D | radeon_encoders.c | 345 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup() 349 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; in radeon_panel_mode_fixup() 350 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; in radeon_panel_mode_fixup()
|
H A D | rs690.c | 251 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust() 254 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust() 309 b.full = dfixed_const(mode->crtc_hdisplay); in rs690_crtc_bandwidth_compute() 359 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); in rs690_crtc_bandwidth_compute() 442 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); in rs690_crtc_bandwidth_compute() 449 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { in rs690_crtc_bandwidth_compute()
|
H A D | radeon_legacy_crtc.c | 82 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); in radeon_legacy_rmx_mode_set() 165 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); in radeon_legacy_rmx_mode_set() 626 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); in radeon_set_crtc_timing()
|
H A D | rv515.c | 984 b.full = dfixed_const(mode->crtc_hdisplay); in rv515_crtc_bandwidth_compute() 1034 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); in rv515_crtc_bandwidth_compute() 1088 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); in rv515_crtc_bandwidth_compute() 1095 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { in rv515_crtc_bandwidth_compute()
|
H A D | radeon_cursor.c | 191 frame_end = crtc->x + crtc->mode.crtc_hdisplay; in radeon_cursor_move_locked()
|
H A D | cik.c | 8801 if (mode->crtc_hdisplay < 1920) { in dce8_line_buffer_adjust() 8804 } else if (mode->crtc_hdisplay < 2560) { in dce8_line_buffer_adjust() 8807 } else if (mode->crtc_hdisplay < 4096) { in dce8_line_buffer_adjust() 9227 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce8_program_watermarks() 9246 wm_high.src_width = mode->crtc_hdisplay; in dce8_program_watermarks() 9286 wm_low.src_width = mode->crtc_hdisplay; in dce8_program_watermarks() 9314 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce8_program_watermarks()
|
H A D | evergreen.c | 2152 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in evergreen_program_watermarks() 2173 wm_high.src_width = mode->crtc_hdisplay; in evergreen_program_watermarks() 2200 wm_low.src_width = mode->crtc_hdisplay; in evergreen_program_watermarks() 2262 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in evergreen_program_watermarks()
|
H A D | si.c | 2301 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce6_program_watermarks() 2326 wm_high.src_width = mode->crtc_hdisplay; in dce6_program_watermarks() 2353 wm_low.src_width = mode->crtc_hdisplay; in dce6_program_watermarks() 2417 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce6_program_watermarks()
|
/dragonfly/sys/dev/drm/include/drm/ |
H A D | drm_modes.h | 355 int crtc_hdisplay; member
|
/dragonfly/sys/dev/drm/ |
H A D | drm_modes.c | 811 *hdisplay = adjusted.crtc_hdisplay; in drm_mode_get_hv_timing() 837 p->crtc_hdisplay = p->hdisplay; in drm_mode_set_crtcinfo() 890 p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay); in drm_mode_set_crtcinfo()
|
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 2394 timing_out->h_addressable = mode_in->crtc_hdisplay; in fill_stream_properties_from_drm_display_mode() 2399 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; in fill_stream_properties_from_drm_display_mode() 2470 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; in copy_crtc_timing_for_drm_display_mode()
|