/dragonfly/contrib/gcc-4.7/gcc/config/i386/ |
H A D | atom.md | 61 ;;; fmul insn can have 4 or 5 cycles latency 65 ;;; fadd can has 5 cycles latency depends on instruction forms 68 ;;; imul insn has 5 cycles latency 374 ;; 2 cycles complex if target is in memory 406 ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored 665 ;; otherwise. 7 cycles average for cvtss2sd 683 ;; otherwise. 8 cycles average for cvtsd2si 724 ;; There will be 3 cycles stall from EX insns to AGAN insns LEA 752 ;; Stall from imul to lea is 8 cycles. 755 ;; Stall from imul to memory address is 8 cycles. [all …]
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H A D | pentium.md | 213 ;; First two cycles of fmul are not pipelined. 220 ;; but only last 2 cycles with FP ones. 233 ;; Integer instructions. Load/execute/store takes 3 cycles, 234 ;; load/execute 2 cycles and execute only one cycle.
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H A D | ppro.md | 57 ;; particular how many cycles they take to be decoded. 80 ;; decoder 0, and this takes an unspecified number of cycles. 203 ;; costly: typically 15 cycles and possibly as many as 26 cycles. 395 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 396 ;; Division by a power of 2 takes only 9 cycles, but we cannot model 564 ;; FIXME: ssediv doesn't close p0 for 17 cycles, surely???
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H A D | k6.md | 51 ;; cycles, including fxcg. 194 ;; two cycles.
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H A D | core2.md | 56 ;; decoder 0, and this takes an unspecified number of cycles. 382 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 383 ;; Division by a power of 2 takes only 9 cycles, but we cannot model
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H A D | athlon.md | 72 ;; Model the fact that double decoded instruction may take 2 cycles 167 ;; Latency of push operation is 3 cycles, but ESP value is available 194 ;; Lea executes in AGU unit with 2 cycles latency. 250 ;; ??? Experiments show that the idiv can overlap with roughly 6 cycles
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H A D | bdver1.md | 46 ;; Model the fact that double decoded instruction may take 2 cycles 178 ;; ??? Experiments show that the IDIV can overlap with roughly 6 cycles
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/dragonfly/contrib/gcc-8.0/gcc/config/i386/ |
H A D | atom.md | 61 ;;; fmul insn can have 4 or 5 cycles latency 65 ;;; fadd can has 5 cycles latency depends on instruction forms 68 ;;; imul insn has 5 cycles latency 374 ;; 2 cycles complex if target is in memory 406 ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored 663 ;; otherwise. 7 cycles average for cvtss2sd 681 ;; otherwise. 8 cycles average for cvtsd2si 722 ;; There will be 3 cycles stall from EX insns to AGAN insns LEA 750 ;; Stall from imul to lea is 8 cycles. 753 ;; Stall from imul to memory address is 8 cycles. [all …]
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H A D | slm.md | 45 ;;; fmul insn can have 4 or 5 cycles latency 50 ;;; fadd can has 3 cycles latency depends on instruction forms 55 ;;; imul insn has 3 cycles latency for SI operands 60 ;;; imul has 4 cycles latency for DI operands with 1/2 tput 64 ;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on 263 ;; DF shift (prefixed with 0f) is complex insn with latency of 4 cycles 373 ;; 2 cycles complex if target is in memory 405 ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored 687 ;; otherwise. 4 cycles average for cvtss2sd 705 ;; otherwise. 8 cycles average for cvtsd2si
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H A D | pentium.md | 213 ;; First two cycles of fmul are not pipelined. 220 ;; but only last 2 cycles with FP ones. 233 ;; Integer instructions. Load/execute/store takes 3 cycles, 234 ;; load/execute 2 cycles and execute only one cycle.
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H A D | ppro.md | 57 ;; particular how many cycles they take to be decoded. 80 ;; decoder 0, and this takes an unspecified number of cycles. 203 ;; costly: typically 15 cycles and possibly as many as 26 cycles. 395 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 396 ;; Division by a power of 2 takes only 9 cycles, but we cannot model 564 ;; FIXME: ssediv doesn't close p0 for 17 cycles, surely???
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H A D | k6.md | 50 ;; cycles, including fxcg. 193 ;; two cycles.
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H A D | bdver3.md | 23 ;; processors. Fetching is done every two cycles rather than every cycle 25 ;; four instructions in two cycles. 40 ;; Double decoded instructions take two cycles whereas 49 ;; Double instructions take two cycles to decode.
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H A D | core2.md | 56 ;; decoder 0, and this takes an unspecified number of cycles. 382 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 383 ;; Division by a power of 2 takes only 9 cycles, but we cannot model
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H A D | haswell.md | 312 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 313 ;; Division by a power of 2 takes only 9 cycles, but we cannot model
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H A D | athlon.md | 71 ;; Model the fact that double decoded instruction may take 2 cycles 166 ;; Latency of push operation is 3 cycles, but ESP value is available 193 ;; Lea executes in AGU unit with 2 cycles latency. 249 ;; ??? Experiments show that the idiv can overlap with roughly 6 cycles
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H A D | bdver1.md | 46 ;; Model the fact that double decoded instruction may take 2 cycles 182 ;; ??? Experiments show that the IDIV can overlap with roughly 6 cycles
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/dragonfly/contrib/gdb-7/gdb/regformats/ |
H A D | reg-bfin.dat | 47 32:cycles
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/dragonfly/contrib/libpcap/ |
H A D | pcap-dpdk.c | 266 uint64_t cycles; in calculate_timestamp() local 269 cycles = rte_get_timer_cycles() - helper->start_cycles; in calculate_timestamp() 270 cur_time.tv_sec = (time_t)(cycles/helper->hz); in calculate_timestamp() 271 cur_time.tv_usec = (suseconds_t)((cycles%helper->hz)*1e6/helper->hz); in calculate_timestamp()
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/dragonfly/sys/net/ |
H A D | if_poll.c | 825 int i, cycles; in rxpoll_handler() local 850 cycles = (io_ctx->residual_burst < io_ctx->poll_each_burst) ? in rxpoll_handler() 852 io_ctx->residual_burst -= cycles; in rxpoll_handler() 892 rec->poll_func(ifp, rec->arg, cycles); in rxpoll_handler()
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/dragonfly/contrib/binutils-2.34/gprof/ |
H A D | fsf_callg_bl.m | 76 If there are any cycles (circles) in the call graph, there is an
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/dragonfly/contrib/binutils-2.27/gprof/ |
H A D | fsf_callg_bl.m | 76 If there are any cycles (circles) in the call graph, there is an
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/dragonfly/contrib/file/magic/Magdir/ |
H A D | c64 | 186 >0x10 lelong x Length:%u cycles
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/dragonfly/sys/vfs/hammer2/ |
H A D | DESIGN | 407 to new blocks except for the volume header (which cycles through 4 copies), 414 blocks (approximately 4MB for every 2GB of storage), and also cycles through 640 implementation reserves 8 copies of every freemap block and cycles through 670 care at all) and once the old data cycles out of the snapshots, or you also 698 cycles (with some care to ensure that all four volume headers
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/dragonfly/contrib/gcc-4.7/gcc/ |
H A D | haifa-sched.c | 569 int cycles; member 684 record_delay_slot_pair (rtx i1, rtx i2, int cycles, int stages) in record_delay_slot_pair() argument 691 p->cycles = cycles; in record_delay_slot_pair() 734 return p->cycles; in pair_delay()
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