Home
last modified time | relevance | path

Searched refs:dclk_table (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega10_hwmgr.h152 struct vega10_single_dpm_table dclk_table; member
H A Dvega12_hwmgr.h131 struct vega12_single_dpm_table dclk_table; member
H A Dvega12_hwmgr.c616 dpm_table = &(data->dpm_table.dclk_table); in vega12_setup_default_dpm_tables()
1046 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; in vega12_upload_dpm_min_level()
1114 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; in vega12_upload_dpm_max_level()
2002 dpm_table = &(data->dpm_table.dclk_table); in vega12_apply_clocks_adjust_rules()
H A Dvega10_hwmgr.c1357 data->dpm_table.dclk_table.count = 0; in vega10_setup_default_dpm_tables()
1372 dpm_table = &(data->dpm_table.dclk_table); in vega10_setup_default_dpm_tables()
1986 &(data->dpm_table.dclk_table); in vega10_populate_smc_uvd_levels()