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Searched refs:dpll (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_display.c522 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
1526 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
6401 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
6406 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
6784 const struct dpll *dpll) in vlv_force_pll_on() argument
6795 pipe_config->dpll = *dpll; in vlv_force_pll_on()
6834 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
6892 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
6908 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
6936 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
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H A Dintel_dpll_mgr.h111 uint32_t dpll; member
277 void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
H A Dintel_dvo.c444 uint32_t dpll[I915_MAX_PIPES]; in intel_dvo_init() local
477 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
478 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
485 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
H A Dintel_drv.h344 struct dpll { struct
700 struct dpll dpll; member
1437 const struct dpll *dpll);
1476 struct dpll *best_clock);
1477 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dintel_dpll_mgr.c350 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
385 I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
396 I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
453 hw_state->dpll, in ibx_dump_hw_state()
1674 struct dpll best_clock; in bxt_ddi_hdmi_pll_dividers()
2500 void intel_release_shared_dpll(struct intel_shared_dpll *dpll, in intel_release_shared_dpll() argument
2507 shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe); in intel_release_shared_dpll()
2528 hw_state->dpll, in intel_dpll_dump_hw_state()
H A Dintel_dp.c55 struct dpll dpll; member
510 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { in vlv_power_sequencer_kick()
1507 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
H A Dintel_sdvo.c1096 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
H A Dintel_ddi.c1456 struct dpll clock; in bxt_calc_pll_link()
H A Di915_drv.h694 struct dpll;