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Searched refs:max_limits (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dbtc_dpm.c1280 max_limits->sclk, in btc_adjust_clock_combinations()
1287 max_limits->mclk, in btc_adjust_clock_combinations()
2132 ps->low.mclk = max_limits->mclk; in btc_apply_state_adjust_rules()
2134 ps->low.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2136 ps->low.vddc = max_limits->vddc; in btc_apply_state_adjust_rules()
2161 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in btc_apply_state_adjust_rules()
2197 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in btc_apply_state_adjust_rules()
2199 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in btc_apply_state_adjust_rules()
2233 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, in btc_apply_state_adjust_rules()
2235 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, in btc_apply_state_adjust_rules()
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H A Dni_dpm.c789 struct radeon_clock_and_voltage_limits *max_limits; in ni_apply_state_adjust_rules() local
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
813 ps->performance_levels[i].vddc = max_limits->vddc; in ni_apply_state_adjust_rules()
815 ps->performance_levels[i].vddci = max_limits->vddci; in ni_apply_state_adjust_rules()
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
864 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
869 btc_adjust_clock_combinations(rdev, max_limits, in ni_apply_state_adjust_rules()
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H A Dbtc_dpm.h45 const struct radeon_clock_and_voltage_limits *max_limits,
H A Dci_dpm.c834 struct radeon_clock_and_voltage_limits *max_limits; in ci_apply_state_adjust_rules() local
859 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
861 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
865 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()
866 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()
867 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
868 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
3965 const struct radeon_clock_and_voltage_limits *max_limits; in ci_enable_uvd_dpm() local
4014 const struct radeon_clock_and_voltage_limits *max_limits; in ci_enable_vce_dpm() local
4047 const struct radeon_clock_and_voltage_limits *max_limits;
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H A Dsi_dpm.c2970 struct radeon_clock_and_voltage_limits *max_limits; in si_apply_state_adjust_rules() local
3035 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3036 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3037 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3038 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3039 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3040 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3041 if (ps->performance_levels[i].vddci > max_limits->vddci) in si_apply_state_adjust_rules()
3042 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
3147 btc_adjust_clock_combinations(rdev, max_limits, in si_apply_state_adjust_rules()
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H A Dkv_dpm.c2147 struct radeon_clock_and_voltage_limits *max_limits = in kv_apply_state_adjust_rules() local
2158 mclk = max_limits->mclk; in kv_apply_state_adjust_rules()
2162 stable_p_state_sclk = (max_limits->sclk * 75) / 100; in kv_apply_state_adjust_rules()
2281 struct radeon_clock_and_voltage_limits *max_limits = in kv_calculate_nbps_level_settings() local
2283 u32 mclk = max_limits->mclk; in kv_calculate_nbps_level_settings()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega10_hwmgr.c3129 max_limits = adev->pm.ac_power ? in vega10_apply_state_adjust_rules()
3137 max_limits->mclk) in vega10_apply_state_adjust_rules()
3139 max_limits->mclk; in vega10_apply_state_adjust_rules()
3141 max_limits->sclk) in vega10_apply_state_adjust_rules()
3143 max_limits->sclk; in vega10_apply_state_adjust_rules()
3161 stable_pstate_sclk = (max_limits->sclk * in vega10_apply_state_adjust_rules()
3177 stable_pstate_mclk = max_limits->mclk; in vega10_apply_state_adjust_rules()
3202 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()
3206 max_limits->mclk : minimum_clocks.memoryClock; in vega10_apply_state_adjust_rules()
4076 info->engine_max_clock = max_limits->sclk; in vega10_get_dal_power_level()
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H A Dsmu7_hwmgr.c2896 const struct phm_clock_and_voltage_limits *max_limits; in smu7_apply_state_adjust_rules() local
2911 max_limits = adev->pm.ac_power ? in smu7_apply_state_adjust_rules()
2919 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
2921 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
2930 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in smu7_apply_state_adjust_rules()
2931 stable_pstate_sclk = (max_limits->sclk * 75) / 100; in smu7_apply_state_adjust_rules()
2946 stable_pstate_mclk = max_limits->mclk; in smu7_apply_state_adjust_rules()
2972 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()
2973 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()
2976 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? in smu7_apply_state_adjust_rules()
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H A Dvega12_hwmgr.c1600 struct phm_clock_and_voltage_limits *max_limits = in vega12_get_dal_power_level()
1603 info->engine_max_clock = max_limits->sclk; in vega12_get_dal_power_level()
1604 info->memory_max_clock = max_limits->mclk; in vega12_get_dal_power_level()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c3299 max_limits->sclk, in btc_adjust_clock_combinations()
3306 max_limits->mclk, in btc_adjust_clock_combinations()
3429 struct amdgpu_clock_and_voltage_limits *max_limits; in si_apply_state_adjust_rules() local
3494 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3495 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3496 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3497 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3499 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3501 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
3606 btc_adjust_clock_combinations(adev, max_limits, in si_apply_state_adjust_rules()
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