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Searched refs:mmTC_CFG_L2_LOAD_POLICY0 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2127 #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d macro
H A Dgfx_7_2_d.h2148 #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d macro
H A Dgfx_8_0_d.h2340 #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d macro
H A Dgfx_8_1_d.h2319 #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1698 #define mmTC_CFG_L2_LOAD_POLICY0 … macro
H A Dgc_9_1_offset.h2012 #define mmTC_CFG_L2_LOAD_POLICY0 … macro
H A Dgc_9_2_1_offset.h1952 #define mmTC_CFG_L2_LOAD_POLICY0 … macro