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Searched refs:mmVCE_CLOCK_GATING_A (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h26 #define mmVCE_CLOCK_GATING_A 0x80BE macro
H A Dvce_2_0_d.h47 #define mmVCE_CLOCK_GATING_A 0x80be macro
H A Dvce_3_0_d.h47 #define mmVCE_CLOCK_GATING_A 0x80be macro
H A Dvce_4_0_offset.h92 #define mmVCE_CLOCK_GATING_A … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c534 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v3_0_mc_resume()
764 uint32_t data = RREG32(mmVCE_CLOCK_GATING_A); in vce_v3_0_set_clockgating_state()
767 WREG32(mmVCE_CLOCK_GATING_A, data); in vce_v3_0_set_clockgating_state()
832 data = RREG32(mmVCE_CLOCK_GATING_A); in vce_v3_0_get_clockgating_state()
H A Dvce_v4_0.c605 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); in vce_v4_0_mc_resume()
905 uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A);
908 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data);