Searched refs:mmVCE_LMI_CACHE_CTRL (Results 1 – 6 of 6) sorted by relevance
| /dragonfly/sys/dev/drm/amd/include/asic_reg/vce/ |
| H A D | vce_1_0_d.h | 28 #define mmVCE_LMI_CACHE_CTRL 0x83BD macro
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| H A D | vce_2_0_d.h | 66 #define mmVCE_LMI_CACHE_CTRL 0x853d macro
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| H A D | vce_3_0_d.h | 71 #define mmVCE_LMI_CACHE_CTRL 0x85bd macro
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| H A D | vce_4_0_offset.h | 144 #define mmVCE_LMI_CACHE_CTRL … macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | vce_v4_0.c | 242 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0); in vce_v4_0_sriov_start()
611 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1); in vce_v4_0_mc_resume()
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| H A D | vce_v3_0.c | 540 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v3_0_mc_resume()
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