Searched refs:mmVCE_STATUS (Results 1 – 6 of 6) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | vce_v4_0.c | 131 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded() 299 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start() 306 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start() 311 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start() 360 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK, in vce_v4_0_start() 372 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); in vce_v4_0_start() 393 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); in vce_v4_0_stop() 710 if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { 715 if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
|
H A D | vce_v3_0.c | 242 uint32_t status = RREG32(mmVCE_STATUS); in vce_v3_0_firmware_loaded() 352 WREG32(mmVCE_STATUS, 0); in vce_v3_0_stop() 630 if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { in vce_v3_0_check_soft_reset() 635 if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { in vce_v3_0_check_soft_reset()
|
/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/ |
H A D | vce_1_0_d.h | 49 #define mmVCE_STATUS 0x8001 macro
|
H A D | vce_2_0_d.h | 27 #define mmVCE_STATUS 0x8001 macro
|
H A D | vce_3_0_d.h | 27 #define mmVCE_STATUS 0x8001 macro
|
H A D | vce_4_0_offset.h | 28 #define mmVCE_STATUS … macro
|