| /dragonfly/sys/dev/drm/amd/display/dc/core/ |
| H A D | dc_debug.c | 142 plane_state->tiling_info.gfx8.num_banks, in pre_surface_trace()
143 plane_state->tiling_info.gfx8.bank_width, in pre_surface_trace()
144 plane_state->tiling_info.gfx8.bank_width_c, in pre_surface_trace()
145 plane_state->tiling_info.gfx8.bank_height, in pre_surface_trace()
147 plane_state->tiling_info.gfx8.tile_aspect, in pre_surface_trace()
149 plane_state->tiling_info.gfx8.tile_split, in pre_surface_trace()
150 plane_state->tiling_info.gfx8.tile_split_c, in pre_surface_trace()
151 plane_state->tiling_info.gfx8.tile_mode, in pre_surface_trace()
162 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
163 plane_state->tiling_info.gfx8.array_mode, in pre_surface_trace()
[all …]
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| H A D | dc.c | 1151 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, in get_plane_info_update_type()
1157 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) in get_plane_info_update_type()
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| /dragonfly/sys/dev/drm/amd/display/dc/inc/hw/ |
| H A D | hubp.h | 81 union dc_tiling_info *tiling_info,
95 union dc_tiling_info *tiling_info,
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| H A D | mem_input.h | 137 union dc_tiling_info *tiling_info,
151 union dc_tiling_info *tiling_info,
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| /dragonfly/sys/dev/drm/amd/display/dc/dce/ |
| H A D | dce_mem_input.c | 101 union dc_tiling_info *tiling_info) in get_mi_tiling() argument
103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
136 union dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
141 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
507 union dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
516 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce110/ |
| H A D | dce110_mem_input_v.c | 530 union dc_tiling_info *tiling_info, in get_dvmm_hw_setting() argument
548 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
571 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_pte_vm() argument
575 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); in dce_mem_input_v_program_pte_vm()
576 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); in dce_mem_input_v_program_pte_vm()
645 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_surface_config() argument
654 program_tiling(mem_input110, tiling_info, format); in dce_mem_input_v_program_surface_config()
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| H A D | dce110_hw_sequencer.c | 1860 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
2656 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce110_program_front_end_for_pipe()
2665 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
2677 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
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| /dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 2079 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); in fill_plane_attributes_from_fb()
2093 plane_state->tiling_info.gfx8.array_mode = in fill_plane_attributes_from_fb()
2099 plane_state->tiling_info.gfx8.tile_mode = in fill_plane_attributes_from_fb()
2106 plane_state->tiling_info.gfx8.pipe_config = in fill_plane_attributes_from_fb()
2114 plane_state->tiling_info.gfx9.num_pipes = in fill_plane_attributes_from_fb()
2116 plane_state->tiling_info.gfx9.num_banks = in fill_plane_attributes_from_fb()
2118 plane_state->tiling_info.gfx9.pipe_interleave = in fill_plane_attributes_from_fb()
2124 plane_state->tiling_info.gfx9.num_rb_per_se = in fill_plane_attributes_from_fb()
2126 plane_state->tiling_info.gfx9.swizzle = in fill_plane_attributes_from_fb()
2128 plane_state->tiling_info.gfx9.shaderEnable = 1; in fill_plane_attributes_from_fb()
[all …]
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| /dragonfly/sys/dev/drm/amd/display/dc/ |
| H A D | dc.h | 477 union dc_tiling_info tiling_info; member
518 union dc_tiling_info tiling_info; member
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_gem.c | 487 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
497 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
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| /dragonfly/sys/dev/drm/include/uapi/drm/ |
| H A D | amdgpu_drm.h | 349 __u64 tiling_info; member
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| /dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hubp.c | 484 union dc_tiling_info *tiling_info, in hubp1_program_surface_config() argument
491 hubp1_program_tiling(hubp, tiling_info, format); in hubp1_program_surface_config()
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| H A D | dcn10_hubp.h | 663 union dc_tiling_info *tiling_info,
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| H A D | dcn10_hw_sequencer.c | 2100 &plane_state->tiling_info, in update_dchubp_dpp()
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| /dragonfly/sys/dev/drm/amd/display/dc/calcs/ |
| H A D | dcn_calcs.c | 275 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
284 switch (pipe->plane_state->tiling_info.gfx9.swizzle) { in pipe_ctx_to_e2e_pipe_params()
935 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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