| /dragonfly/sys/dev/drm/ |
| H A D | drm_vblank.c | 96 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in store_vblank() local
192 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in drm_update_vblank_count() local
276 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in drm_vblank_count() local
299 u32 vblank; in drm_crtc_accurate_vblank_count() local
338 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in drm_vblank_disable_and_save() local
434 struct drm_vblank_crtc *vblank = &dev->vblank[i]; in drm_vblank_init() local
1122 pipe, vblank->enabled, vblank->inmodeset); in drm_crtc_vblank_off()
1218 pipe, vblank->enabled, vblank->inmodeset); in drm_crtc_vblank_on()
1500 vblank = &dev->vblank[pipe]; in drm_wait_vblank_ioctl()
1709 vblank = &dev->vblank[pipe]; in drm_crtc_get_sequence_ioctl()
[all …]
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| H A D | drm_irq.c | 194 struct drm_vblank_crtc *vblank = &dev->vblank[i]; in drm_irq_uninstall() local
196 if (!vblank->enabled) in drm_irq_uninstall()
202 wake_up(&vblank->queue); in drm_irq_uninstall()
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| H A D | drm_edid.c | 2208 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; in drm_mode_detailed() local
2258 mode->vtotal = mode->vdisplay + vblank; in drm_mode_detailed()
4553 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; in drm_mode_displayid_detailed() local
4571 mode->vtotal = mode->vdisplay + vblank; in drm_mode_displayid_detailed()
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| H A D | drm_atomic_helper.c | 1243 ret = wait_event_timeout(dev->vblank[i].queue, in drm_atomic_helper_wait_for_vblanks()
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| /dragonfly/test/debug/ |
| H A D | testvblank.c | 19 union drm_wait_vblank vblank; in main() local
25 bzero(&vblank, sizeof(vblank)); in main()
26 vblank.request.type = _DRM_VBLANK_RELATIVE; in main()
27 vblank.request.sequence = 10; in main()
29 if (ioctl(fd, DRM_IOCTL_WAIT_VBLANK, &vblank) < 0) in main()
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_encoders.c | 153 unsigned vblank = native_mode->vtotal - native_mode->vdisplay; in amdgpu_panel_mode_fixup() local
169 adjusted_mode->vtotal = native_mode->vdisplay + vblank; in amdgpu_panel_mode_fixup()
182 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; in amdgpu_panel_mode_fixup()
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| H A D | dce_v10_0.c | 82 uint32_t vblank; member
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
3200 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
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| H A D | dce_v11_0.c | 84 uint32_t vblank; member
90 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
3327 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | radeon_encoders.c | 320 unsigned vblank = native_mode->vtotal - native_mode->vdisplay; in radeon_panel_mode_fixup() local
338 adjusted_mode->vtotal = native_mode->vdisplay + vblank; in radeon_panel_mode_fixup()
353 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; in radeon_panel_mode_fixup()
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| /dragonfly/sys/dev/drm/i915/ |
| H A D | intel_crt.c | 619 uint32_t vblank, vblank_start, vblank_end; in intel_crt_load_detect() local
637 vblank = I915_READ(vblank_reg); in intel_crt_load_detect()
642 vblank_start = (vblank & 0xfff) + 1; in intel_crt_load_detect()
643 vblank_end = ((vblank >> 16) & 0xfff) + 1; in intel_crt_load_detect()
707 I915_WRITE(vblank_reg, vblank); in intel_crt_load_detect()
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| H A D | intel_fbc.c | 419 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe]; in intel_fbc_work_fn() local
443 wait_event_timeout(vblank->queue, in intel_fbc_work_fn()
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| H A D | i915_irq.c | 738 const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode; in i915_get_vblank_counter()
801 struct drm_vblank_crtc *vblank = in __intel_get_crtc_scanline_from_timestamp() local
802 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in __intel_get_crtc_scanline_from_timestamp()
803 const struct drm_display_mode *mode = &vblank->hwmode; in __intel_get_crtc_scanline_from_timestamp()
847 struct drm_vblank_crtc *vblank; in __intel_get_crtc_scanline() local
854 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in __intel_get_crtc_scanline()
855 mode = &vblank->hwmode; in __intel_get_crtc_scanline()
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| H A D | intel_display.c | 15374 u32 vblank; member
15453 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); in intel_display_capture_error_state()
15513 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); in intel_display_print_error_state()
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| /dragonfly/sys/dev/drm/include/drm/ |
| H A D | drm_displayid.h | 84 u8 vblank[2]; member
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| H A D | drm_device.h | 135 struct drm_vblank_crtc *vblank; member
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