Searched refs:vblank_end (Results 1 – 5 of 5) sorted by relevance
619 uint32_t vblank, vblank_start, vblank_end; in intel_crt_load_detect() local643 vblank_end = ((vblank >> 16) & 0xfff) + 1; in intel_crt_load_detect()669 if (vblank_start <= vactive && vblank_end >= vtotal) { in intel_crt_load_detect()676 ((vblank_end - 1) << 16)); in intel_crt_load_detect()680 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()683 vsample = (vtotal + vblank_end) >> 1; in intel_crt_load_detect()
995 unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params() local1142 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ in dml1_rq_dlg_get_dlg_params()1244 vblank_end); in dml1_rq_dlg_get_dlg_params()
292 unsigned int vblank_end; member
416 input->dest.vblank_end = input->dest.vblank_start in pipe_ctx_to_e2e_pipe_params()1115 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()1141 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; in dcn_validate_bandwidth()
124 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp1_vready_workaround()