/freebsd/sys/dev/ste/ |
H A D | if_ste.c | 211 val = CSR_READ_1(sc, STE_PHYCTL); in ste_mii_bitbang_read() 429 rxcfg = CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter() 453 CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter() 814 CSR_READ_1(sc, STE_STAT_RX_BCAST); in ste_stats_clear() 815 CSR_READ_1(sc, STE_STAT_RX_MCAST); in ste_stats_clear() 816 CSR_READ_1(sc, STE_STAT_RX_LOST); in ste_stats_clear() 821 CSR_READ_1(sc, STE_STAT_TX_BCAST); in ste_stats_clear() 822 CSR_READ_1(sc, STE_STAT_TX_MCAST); in ste_stats_clear() 827 CSR_READ_1(sc, STE_STAT_TX_DEFER); in ste_stats_clear() 829 CSR_READ_1(sc, STE_STAT_TX_ABORT); in ste_stats_clear() [all …]
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H A D | if_stereg.h | 492 #define CSR_READ_1(sc, reg) \ macro
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/freebsd/sys/dev/re/ |
H A D | if_re.c | 359 CSR_READ_1(sc, RL_EECMD) | x) 363 CSR_READ_1(sc, RL_EECMD) & ~x) 1324 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach() 1361 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach() 1559 cfg = CSR_READ_1(sc, sc->rl_cfg1); in re_attach() 1562 cfg = CSR_READ_1(sc, sc->rl_cfg5); in re_attach() 3901 v = CSR_READ_1(sc, sc->rl_cfg1); in re_setwol() 3907 v = CSR_READ_1(sc, sc->rl_cfg3); in re_setwol() 3913 v = CSR_READ_1(sc, sc->rl_cfg5); in re_setwol() 3958 v = CSR_READ_1(sc, sc->rl_cfg3); in re_clrwol() [all …]
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/freebsd/sys/dev/vge/ |
H A D | if_vge.c | 258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_eeprom_getword() 299 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); in vge_read_eeprom() 520 cfg = CSR_READ_1(sc, VGE_RXCFG); in vge_setvlan() 573 rxcfg = CSR_READ_1(sc, VGE_RXCTL); in vge_rxfilter() 1086 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & in vge_attach() 1669 physts = CSR_READ_1(sc, VGE_PHYSTS0); in vge_link_statchg() 2758 intctl = CSR_READ_1(sc, VGE_INTCTL1); in vge_intr_holdoff() 2891 val = CSR_READ_1(sc, VGE_PWRSTAT); in vge_setwol() 2895 val = CSR_READ_1(sc, VGE_PWRSTAT); in vge_setwol() 2913 val = CSR_READ_1(sc, VGE_PWRSTAT); in vge_clrwol() [all …]
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H A D | if_vgevar.h | 228 #define CSR_READ_1(sc, reg) \ macro 232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
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/freebsd/sys/dev/vr/ |
H A D | if_vr.c | 322 cr0 = CSR_READ_1(sc, VR_CR0); in vr_miibus_statchg() 323 cr1 = CSR_READ_1(sc, VR_CR1); in vr_miibus_statchg() 347 fc = CSR_READ_1(sc, VR_FLOWCR1); in vr_miibus_statchg() 2353 cmd = CSR_READ_1(sc, VR_CR0); in vr_tx_start() 2372 cmd = CSR_READ_1(sc, VR_CR0); in vr_rx_start() 2388 cmd = CSR_READ_1(sc, VR_CR0); in vr_tx_stop() 2394 cmd = CSR_READ_1(sc, VR_CR0); in vr_tx_stop() 2410 cmd = CSR_READ_1(sc, VR_CR0); in vr_rx_stop() 2416 cmd = CSR_READ_1(sc, VR_CR0); in vr_rx_stop() 2577 v = CSR_READ_1(sc, VR_STICKHW); in vr_setwol() [all …]
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H A D | if_vrreg.h | 754 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) macro 756 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 757 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
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/freebsd/sys/dev/rl/ |
H A D | if_rl.c | 265 CSR_READ_1(sc, RL_EECMD) | x) 269 CSR_READ_1(sc, RL_EECMD) & ~x) 365 val = CSR_READ_1(sc, RL_MII); in rl_mii_bitbang_read() 422 return (CSR_READ_1(sc, RL_MEDIASTAT)); in rl_miibus_readreg() 776 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); in rl_attach() 1926 if ((CSR_READ_1(sc, RL_COMMAND) & in rl_stop() 2063 v = CSR_READ_1(sc, sc->rl_cfg1); in rl_setwol() 2069 v = CSR_READ_1(sc, sc->rl_cfg3); in rl_setwol() 2075 v = CSR_READ_1(sc, sc->rl_cfg5); in rl_setwol() 2110 v = CSR_READ_1(sc, sc->rl_cfg3); in rl_clrwol() [all …]
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H A D | if_rlreg.h | 958 #define CSR_READ_1(sc, reg) \ macro 965 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 968 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
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/freebsd/sys/dev/ipw/ |
H A D | if_ipwreg.h | 326 #define CSR_READ_1(sc, reg) \ macro 353 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
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/freebsd/sys/dev/fxp/ |
H A D | if_fxp.c | 334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) in fxp_scb_wait() 337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); in fxp_scb_wait() 338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); in fxp_scb_wait() 340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), in fxp_scb_wait() 341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), in fxp_scb_wait() 342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); in fxp_scb_wait() 915 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_attach() 1113 CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_resume() 1688 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); in fxp_poll() 2155 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { in fxp_tick() [all …]
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H A D | if_fxpvar.h | 244 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) macro
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/freebsd/sys/dev/xl/ |
H A D | if_xl.c | 453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_miibus_statchg() 625 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90x() 685 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90xB() 814 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_setmode() 2084 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { in xl_txeoc() 2307 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); in xl_stats_update() 2323 CSR_READ_1(sc, XL_W4_BADSSD); in xl_stats_update() 2822 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_init_locked() 2948 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts() 2957 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
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H A D | if_xlreg.h | 663 #define CSR_READ_1(sc, reg) \ macro
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/freebsd/sys/dev/msk/ |
H A D | if_msk.c | 1204 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; in mskc_setup_rambuffer() 1663 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); in msk_attach() 1777 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); in mskc_attach() 1778 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; in mskc_attach() 1816 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); in mskc_attach() 1819 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in mskc_attach() 3836 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_init_locked() 4091 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer() 4106 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); in msk_set_rambuffer() 4229 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == in msk_stop() [all …]
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H A D | if_mskreg.h | 2135 #define CSR_READ_1(sc, reg) \ macro 2157 CSR_READ_1((sc_if)->msk_softc, (reg))
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/freebsd/sys/dev/stge/ |
H A D | if_stge.c | 255 val = CSR_READ_1(sc, STGE_PhyCtrl); in stge_mii_bitbang_read() 294 error = CSR_READ_1(sc, STGE_PhyCtrl); in stge_miibus_readreg() 591 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach() 989 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_setwol() 1035 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_resume() 1957 v = CSR_READ_1(sc, STGE_PhySet); in stge_reset()
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H A D | if_stgereg.h | 100 #define CSR_READ_1(_sc, reg) \ macro
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/freebsd/sys/dev/my/ |
H A D | if_myreg.h | 399 #define CSR_READ_1(sc, reg) \ macro
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H A D | if_my.c | 853 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); in my_attach()
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/freebsd/sys/dev/lge/ |
H A D | if_lge.c | 649 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) in lge_list_rx_init() 969 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); in lge_txeof() 1168 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) in lge_start_locked()
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H A D | if_lgereg.h | 547 #define CSR_READ_1(sc, reg) \ macro
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/freebsd/sys/dev/iwi/ |
H A D | if_iwireg.h | 572 #define CSR_READ_1(sc, reg) \ macro
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/freebsd/sys/dev/sk/ |
H A D | if_skreg.h | 1285 #define CSR_READ_1(sc, reg) \ macro
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H A D | if_sk.c | 387 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); in sk_win_read_1() 389 return(CSR_READ_1(sc, reg)); in sk_win_read_1()
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